Table 4-11 Quad Timer A Registers Address Map (Continued)
(TMRA_BASE = $00 F040)
Register Acronym
Address Offset
Register Description
Compare Register 2
TMRA0_CMP2
TMRA0_CAP
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
Capture Register
TMRA0_LOAD
TMRA0_HOLD
TMRA0_CNTR
TMRA0_CTRL
TMRA0_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRA0_CMPLD1
TMRA0_CMPLD2
TMRA0_COMSCR
TMRA1_CMP1
TMRA1_CMP2
TMRA1_CAP
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
Compare Register 1
Compare Register 2
Capture Register
TMRA1_LOAD
TMRA1_HOLD
TMRA1_CNTR
TMRA1_CTRL
TMRA1_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRA1_CMPLD1
TMRA1_CMPLD2
TMRA1_COMSCR
TMRA2_CMP1
TMRA2_CMP2
TMRA2_CAP
$20
$21
$22
$23
$24
$25
$26
$27
$28
Compare Register 1
Compare Register 2
Capture Register
TMRA2_LOAD
TMRA2_HOLD
TMRA2_CNTR
TMRA2_CTRL
TMRA2_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
TMRA2_CMPLD1
56F8345 Technical Data, Rev. 17
50
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
