3.11 JTAG Timing
1, 3
Table 3-16 JTAG Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic
TCK frequency of operation2
Symbol
fOP
Min
DC
100
50
Max
10
Unit
MHz
ns
TCK cycle time
tCY
—
TCK clock pulse width
TMS, TDI data setup time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO tri-state
TRST assertion time
DE assertion time
tPW
—
ns
tDS
0.4
1.2
—
—
ns
tDH
—
ns
tDV
26.6
23.5
—
ns
tTS
—
ns
tTRST
tDE
50
ns
8T
—
ns
1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz
operation, T = 12.5ns.
2. TCK frequency of operation must be less than 1/8 the processor rate.
3. Parameters listed are guaranteed by design.
tCY
tPW
tPW
VIH
VM
VIL
VM
TCK
(Input)
VM = VIL + (VIH – VIL)/2
Figure 3-27 Test Clock Input Timing Diagram
56F801 Technical Data, Rev. 17
38
Freescale Semiconductor
FREESCALE [ Freescale ]
