Interrupts
Maximum Delay = 64 MSTR_OSC cycles for POR reset extension and 32 MSTR_OSC cycles
for combined reset extension
RST
MSTR_OSC
Switch on falling OSC_CLK
96 MSTR_OSC cycles
CKGEN_RST
SYS_CLK_x2
SYS_CLK
SYS_CLK_D
SYS_CLK_DIV2
32 SYS_CLK cycles delay
Switch on falling SYS_CLK
PERIP_RST
CORE_RST
Switch on falling SYS_CLK
32 SYS_CLK cycles delay
Figure 6-16 Timing Relationships of Reset Signal to Clocks
6.8 Interrupts
The SIM generates no interrupts.
Part 7 Security Features
The 56F8014 offers security features intended to prevent unauthorized users from reading the contents of
the Flash Memory (FM) array. The 56F8014’s Flash security consists of several hardware interlocks that
prevent unauthorized users from gaining access to the Flash array.
Note, however, that part of the security must lie with the user’s code. An extreme example would be user’s
code that includes a subroutine to read and transfer the contents of the internal program to SCI, SPI or
another peripheral, as this code would defeat the purpose of security. At the same time, the user may also
wish to put a “backdoor” in his program. As an example, the user downloads a security key through the
SCI, allowing access to a programming routine that updates parameters stored in another section of the
Flash.
56F8014 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
81
FREESCALE [ Freescale ]
