Resets
EXTENDED_POR
JTAG
POR
pulse shaper
Power-On
Reset
Memory
(active
low)
Subsystem
Delay 64
MSTR_OSC
Clocks
CLKGEN_RST
OCCS
COMBINED_RST
External
RESET IN
(active
PERIP_RST
Delay 32
MSTR_OSC
Clocks
RESET
Peripherals
low)
pulse shaper
Delay 32
COP
(active
low)
sys clocks
SW Reset
56800E
pulse shaper
Delay 32
sys clocks
pulse shaper
Delay blocks assert immediately and
deassert only after the programmed
number of clock cycles.
CORE_RST
Figure 6-15 Sources of RESET Functional Diagram (Test modes not included)
POR resets are extended 64 MSTR_OSC clocks to stabilize the power supply. All resets are subsequently
extended for an additional 32 MSTR_OSC clocks and 64 system clocks as the various internal reset
controls are released. Given the normal relaxation oscillator rate of 8MHz, the duration of a POR reset
from when power comes on to when code is running is 28μS. An external reset generation chip may also
be used. Resets may be asserted asynchronously, but they are always released internally on a rising edge
of the system clock.
56F8014 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
79
FREESCALE [ Freescale ]
