Register Descriptions
5.6.2.8
PLL Loss of Reference or Change in Lock Status Interrupt Priority Level
(PLL IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3
Interrupt Priority Register 2 (IPR2)
Base + $2
Read
15
14
13
12
11
0
10
0
9
8
7
6
5
4
3
2
1
0
SCI_RERR
IPL
SCI_RCV IPL
SCI_TIDL IPL SCI_XMIT IPL SPI_XMIT IPL SPI_RCV IPL
GPIOA IPL
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-5 Interrupt Priority Register 2 (IPR2)
5.6.3.1
SCI Receiver Full Interrupt Priority Level (SCI_RCV IPL)—
Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3.2
SCI Receiver Error Interrupt Priority Level (SCI_RERR IPL)—
Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3.3
Reserved—Bits 11–10
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
56F8014 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
51
FREESCALE [ Freescale ]
