ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions 8.0 V ≤ VPWR = VSUP ≤ 40 V, -40°C ≤ TA ≤ 135°C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUTS
VPWR Supply Voltage Startup Threshold(10)
VPWR_ST
ISUP
–
6.0
8.0
V
VSUP Supply Current, VPWR = VSUP = 40 V
RST and ENABLE = 5.0 V
mA
No output loads on Gate Drive Pins, No PWM
No output loads on Gate Drive Pins, 20 kHz, 50% Duty Cycle
–
–
1.0
–
–
10
VPWR Supply Current, VPWR = VSUP = 40 V
RST and ENABLE = 5.0 V
IPWR_ON
mA
µA
No output loads on Gate Drive Pins, No PWM, Outputs initialized
–
–
11
–
20
95
Output Loads = 620 nC per FET, 20 kHz PWM(11)
Sleep State Supply Current, RST = 0 V
V
SUP = 40 V
ISUP
–
–
14
56
30
VPWR = 40 V
IPWR
100
Sleep State Output Gate Voltage
IG < 100 µA
VGATESS
V
V
–
–
1.3
Trickle Charge Pump (Bootstrap Voltage)
VBoot
V
SUP = 14 V
22
–
28
–
32
Bootstrap Diode Forward Voltage at 10 mA
VF
VDD
IDD
1.2
V
V
VDD INTERNAL REGULATOR
VDD Output Voltage, VPWR = 8 to 40 V, C = 0.47 µF(12)
External Load IDD_EXT = 0 to 1.0 mA
4.5
–
–
–
5.5
12
Internal VDD Supply Current, VDD = 5.5 V, No External Load
mA
VLS REGULATOR
Peak Output Current, V
Linear Regulator Output Voltage, IVLS = 0 to 60 mA(13)
VLS Disable Threshold(14)
= 16 V, VLS = 10 V
IPEAK
VLS
350
13.5
7.5
600
15
800
17
mA
V
PWR
VTHVLS
8.0
8.5
V
Notes
10. Operation with the Charge Pump is recommended when minimum system voltage could be less than 14 V. VPWR must exceed this
threshold in order for the Charge Pump and VDD regulator to startup and drive VPWR to > 8.0 V. Once VPWR exceeds 8.0 V, the circuits
will continue to operate even if system voltage drops below 6.0 V.
11. This parameter is guaranteed by design. It is not production tested.
12. Minimum external capacitor for stable VDD operation is 0.47 µF.
13. Recommended external capacitor for the VLS regulator is 2.2 µF low ESR at each pin VLS and VLS_CAP.
14. When VLS is less than this value, the outputs are disabled and HOLDOFF circuits are active. Recovery is automatic when VLS rises
above this threshold again. A filter delay of approximately 700 ns on the comparator output eliminates responses to spurious transients
on VLS
.
33937
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
FREESCALE [ Freescale ]
