PIN CONNECTIONS
Table 2. 33937 Pin Definitions (continued)
A functional description of each pin can be found in the
Functional Pin Description
section beginning on
page 23.
Pin
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30, 31
32
34
35
36
37
38
39
40
41
42
43
44
Pin Name
PA_HS
PA_LS
VDD
PB_HS
PB_LS
INT
CS
SI
SCLK
SO
PC_LS
PC_HS
AMP_OUT
AMP_N
AMP_P
OC_OUT
OC_TH
VSS
GND
VLS_CAP
PC_LS_S
PC_LS_G
PC_HS_S
PC_HS_G
PC_BOOT
PB_LS_S
PB_LS_G
PB_HS_S
PB_HS_G
PB_BOOT
PA_LS_S
Pin Function
Digital Input
Digital Input
Analog Output
Digital Input
Digital Input
Digital Output
Digital Input
Digital Input
Digital Input
Digital Output
Digital Input
Digital Input
Analog Output
Analog Input
Analog Input
Digital Output
Formal Name
Phase A High Side
Phase A Low Side
VDD Regulator
Phase B High Side
Phase B Low Side
Interrupt
Chip Select
Serial In
Serial Clock
Serial Out
Phase C Low Side
Phase C High Side
Amplifier Output
Amplifier Invert
Amplifier Non-Invert
Over-current Out
Definition
Active low input logic signal enables the High Side Driver for Phase A
Active high input logic signal enables the Low Side Driver for Phase A
VDD regulator output capacitor connection.
Active low input logic signal enables the High Side Driver for Phase B
Active high input logic signal enables the Low Side Driver for Phase B
Interrupt pin output
Chip Select input. It frames SPI commands and enables SPI port
Input data for SPI port. Clocked on the falling edge of SCLK, MSB first
Clock for SPI port and typically is 3.0 MHz
Output data for SPI port. Tri-state until CS becomes low
Active high input logic signal enables the Low Side Driver for Phase C
Active low input logic signal enables the High Side Driver for Phase C
Output of the current-sensing amplifier
Inverting input of the current-sensing amplifier
Non-inverting input of the current-sensing amplifier
Totem pole digital output of the Over-current Comparator
Analog Input Over-current Threshold Threshold of the over-current detector
Ground
Ground
Voltage Source Supply Ground reference for logic interface and power supplies
Ground
Substrate and ESD reference, connect to VSS
VLS Regulator connection for additional output capacitor, providing low
impedance supply source for Low Side Gate Drive
Source connection for Phase C Low Side FET
Analog Output VLS Regulator Output
Capacitor
Power Input
Phase C Low Side
Source
Power Output Phase C Low Side Gate Gate drive output for Phase C Low Side
Drive
Power Input
Power Output
Analog Input
Power Input
Phase C High Side
Source
Phase C High Side
Gate Drive
Phase C Bootstrap
Phase B Low Side
Source
Source connection for Phase C High Side FET
Gate Drive for output Phase C High Side FET
Bootstrap capacitor for Phase C
Source connection for Phase B Low Side FET
Power Output Phase B Low Side Gate Gate Drive for output Phase B Low Side
Drive
Power Input
Power Output
Analog Input
Power Input
Phase B High Side
Source
Phase B High Side
Gate Drive
Phase B Bootstrap
Phase A Low Side
Source
Source connection for Phase B High Side FET
Gate Drive for output Phase B High Side
Bootstrap capacitor for Phase B
Source connection for Phase A Low Side FET
33937
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
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