FUNCTIONAL INTERNAL BLOCK DESCRIPTION
complementary output to immediately turn off and the
selected one to turn on after the deadtime delay as illustrated
in Figure 16. The deadtime delay timer starts when the
corresponding FET was commanded off (see Figure 6 and
Figure 16).
during periods of reduced current. Current limit is blanked
immediately after subsequent input state change in order to
ensure device stays off during dV/dt transients.
HIGH SIDE DRIVERS
These three drivers switch the voltage across the
bootstrap capacitor to the external High Side FETs. The
circuits provide a low-impedance drive to the gate, ensuring
the FETs remain off in the presence of high dV/dt transients
on their sources. Further, these output drivers isolate the
other portions of the IC from currents capable of being
injected into the substrate due to rapid dV/dt transients on the
FETs.
PA _HS
PA_LS
Deadtime
Delay
The High Side drivers deliver power from their bootstrap
capacitor to the gate of the external High Side FET, thus
turning the High Side FET on. The High Side driver uses a
level shifter, which allows the gate of the external High Side
FET to be turned off by switching to the High Side FET
source.
PA_HS_G
PA_LS_G
Figure 16. Edge Sensitive Logic Inputs (Phase A)
BOOTSTRAP SUPPLY (VLS)
The gate supply voltage for the High Side drivers is
obtained from the bootstrap supply, so, a short time is
required after the application of power to the IC to charge the
bootstrap capacitors. To ensure this occurrence, the internal
control logic will not allow a High Side switch to be turned on
after entering the ENABLE state until the corresponding Low
Side switch is enabled at least once. Caution must be
exercised after a long period of inactivity of the Low Side
switches to verify the bootstrap capacitor is not discharged. It
will be charged by activating the Low Side switches for a brief
period, or by attaching external bleed resistors from the
HS_S pins to GND.
This is the portion of the IC providing current to recharge
the bootstrap capacitors. It also supplies the peak currents
required for the Low Side gate drivers.
The power for the gate drive circuits is provided by VLS
which is supplied from the VPWR pin. This pin can be
connected to system battery voltage and is capable of
withstanding up to the full load dump voltage of the system.
However, the IC only requires a low-voltage supply on this
pin, typically 13 to 16 V. Higher voltages on this pin will
increase the IC power dissipation.
CAUTION for 33937 only (Use the 33937A to avoid this
CAUTION)
In 12 V systems the supply voltage can fall as low as 6.0 V.
This limits the gate voltage capable of being applied to the
FETs and reduces system performance due to the higher
FET on-resistance. To allow a higher gate voltage to be
supplied, the IC also incorporates a charge pump. The
switches and control circuitry are internal; the capacitors and
diodes are external (see Figure 22).
Using the 33937 in applications which use large value
bootstrap capacitors requires extra care to insure the
transient induced when charging fully depleted capacitors
does not cause an unintended power on reset. The 33937A
has been modified to eliminate the need for these special
considerations. Factors which affect the sensitivity to this
effect are, bootstrap capacitor size, VLS filter capacitor size,
VLS voltage and the junction temperature. The effect is more
pronounced for greater values of these parameters. It is also
more pronounced if all phases charge depleted capacitors
simultaneously. For balanced capacitance on VLS and
VLS_CAP of greater than 3.5 µF (total of 7.0 µF VLS
filtering), 1.2 µF bootstrap capacitance on each phase could
cause a POR at room temperature with VLS at 13 V. At the
worst case conditions of 15.4 V VLS voltage and 150°C
junction temperature, with the same total VLS capacitance of
7.0 µF, approximately 0.3 µF total (0.1µF each) on Px_BOOT
could cause the same effect. Since this characteristic is
intrinsic to the bootstrap diode integrated on the device, a
valid solution to prevent an undesired reset during
LOW SIDE DRIVERS
These three drivers turn on and off the external Low Side
FETs. The circuits provide a low-impedance drive to the gate,
ensuring the FETs remain off in the presence of high dV/dt
transients on their drains. Additionally, these output drivers
isolate the other portions of the IC from currents capable of
being injected into the substrate due to rapid dV/dt transients
on the FET drains.
Low Side drivers switch power from VLS to the gates of the
Low Side FETs. The Low Side drivers are capable of
providing a typical peak current of 2.0 A. This gate drive
current may be limited by external resistors in order to
achieve a good trade-off between the efficiency and EMC
(Electro-Magnetic Compatibility) compliance of the
application. the Low Side driver uses High Side PMOS for
turn on and Low Side isolated LDMOS for turn off. The circuit
ensures the impedance of the driver remains low, even
initialization would be to use external diodes between VLS
and the Px_BOOT pin.
33937
Analog Integrated Circuit Device Data
Freescale Semiconductor
28
FREESCALE [ Freescale ]
