FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC33937 - Functional Block Diagram
Integrated Supply
Main Charge Pump
5V Regulator
Trickle Charge Pump
VLS Regulator
Sensing & Protection
High Side
and
Hold-off
Under-voltage
De-sat
Temperature
Phase
Output
Pre-drivers
Over-current
Logic & Control
Fault Register
Phase Control
Dead Time
Mode Control
SPI Communication
Integrated Supply
Sensing & Protection
Logic& Control
Drivers
Figure 15. Functional Internal Block Description
All functions of the IC can be described as the following
five major functional blocks:
12 µs. Calibration of the delay, because of internal IC
variations, is performed via the SPI.
• Enabling of simultaneous operation of High Side and
Low Side FETs—Normally, both FETs would not be
enabled simultaneously. However, for certain applications
where the load is connected between the High Side and
Low Side FETs, this could be advantageous. If this mode
is enabled, the blanking time delay will be disabled. A
sequence of commands may be required to enable this
function to prevent inadvertent enabling. In addition, this
command can only be executed once after reset to enable
or disable simultaneous turn-on.
•
•
•
•
•
Logic Inputs and Interface
Bootstrap Supply
Low Side Drivers
High Side Drivers
Charge Pump
LOGIC INPUTS AND INTERFACE
This section contains the SPI port, control logic, and shoot-
through timers.
• Setting of various operating modes of the IC and
enabling of interrupt sources.
The IC logic inputs have Schmitt trigger inputs with
hysteresis. Logic inputs are 3.0 V compatible. The logic
outputs are driven from the internal supply of approximately
5.0 V.
The 33937 allows different operating modes to be set and
locked by an SPI command (FULLON, Desaturation Fault,
Zero Deadtime). SPI commands can also determine how
the various faults are (or are not) reported.
The SPI registers and functionality is described completely
in the LOGIC COMMANDS AND REGISTERS section of this
document. SPI functionality includes the following:
• Read back of internal registers.
The status of the 33937 Status Registers can be read back
by the Master (DSP or MCU).
• Programming of deadtime delay—This delay is
adjustable in approximately 50 ns steps from 0 ns to
The Px_HS and Px_LS logic inputs are edge sensitive.
This means the leading edge on an input will cause the
33937
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
FREESCALE [ Freescale ]
