FUNCTIONAL DESCRIPTIONS
INTRODUCTION
A power-on-reset (POR) circuit monitors this pin and until
the voltage rises above the threshold, the internal logic will be
reset; driver outputs will be tri-stated and SPI communication
disabled.
PHASE C HIGH SIDE INPUT (PC_HS)
This input logic pin enables the High Side Driver for Phase
C. This signal is active low, and is pulled up by an internal
current source.
The VDD regulator can be disabled by asserting the RST
signal low. The VDD regulator is powered from the VPWR
pin.
AMPLIFIER OUTPUT (AMP_OUT)
This pin is the output for the current sensing amplifier. It is
also the sense input to the over-current comparator.
PHASE B HIGH SIDE CONTROL INPUT (PB_HS)
This pin is the input logic signal, enabling the High Side
driver for Phase B. The signal is active low, and is pulled up
by an internal current source.
AMPLIFIER INVERTING INPUT (AMP_N)
The inverting input to the current sensing amplifier.
AMPLIFIER NON-INVERTING INPUT (AMP_P)
PHASE B LOW SIDE INPUT (PB_LS)
The non-inverting input to the current sensing amplifier.
This pin is the input logic signal, enabling the Low Side
driver for Phase B. The signal is active high, and is pulled
down by an internal current sink.
OVER-CURRENT COMPARATOR OUTPUT
(OC_OUT)
The over-current comparator output is a totem pole logic
level output. A logic high indicates an over-current condition.
INTERRUPT (INT)
The Interrupt pin is a totem pole logic output. When a fault
is detected, this pin will pull high until it is cleared by
executing the Clear Interrupt command via the SPI port. The
faults capable of causing an interrupt can be masked via the
MASK0 and MASK1 SPI registers to customize the
response.
OVER-CURRENT COMPARATOR THRESHOLD
(OC_TH)
This input sets the threshold level of the over-current
comparator.
CHIP SELECT (CS)
VOLTAGE SOURCE SUPPLY (VSS)
Chip select is a logic input that frames the SPI commands
and enables the SPI port. This signal is active low, and is
pulled up by an internal current source.
VSS is the ground reference for the logic interface and
power supplies.
GROUND (GND0,GND1)
SERIAL IN (SI)
These two pins are connected internally to VSS by a 1.0 Ω
resistor. They provide device substrate connections and also
the primary return path for ESD protection.
The Serial In pin is used to input data to the SPI port.
Clocked on the falling edge of SCLK, it is the most significant
bit (MSB) first. This pin is pulled down by an internal current
sink.
VLS REGULATOR CAPACITOR (VLS_CAP)
This connection is for a capacitor which will provide a low-
impedance for switching currents on the gate drive. A low
ESR decoupling capacitor, capable of sourcing the pulsed
drive currents must be connected between this pin and VSS.
Use the 33937A to avoid the CAUTION on page 28 for
capacitances greater than 3.5 µF.
SERIAL CLOCK (SCLK)
This logic input is the clock is used for the SPI port. The
SCLK typically runs at 3.0 MHz (up to 5.0 MHz) and is pulled
down by an internal current sink.
SERIAL OUT (SO)
This is the same DC node as VLS, but it is physically
placed on the opposite end of the IC to minimize the source
impedance to the gate drive circuits.
Output data for the SPI port streams from this pin. It is tri-
stated until CS is low. New data appears on rising edges of
SCLK in preparation for latching by the falling edge of SCLK
on the master.
PHASE C LOW SIDE SOURCE (PC_LS_S)
The phase C Low Side source is the pin used to return the
gate currents from the Low Side FET. Best performance is
realized by connecting this node directly to the source of the
Low Side FET for phase C.
PHASE C LOW SIDE INPUT (PC_LS)
This input logic pin enables the Low Side Driver for Phase
C. This pin is an active high, and is pulled down by an internal
current sink.
PHASE C LOW SIDE GATE (PC_LS_G)
This is the gate drive for the phase C Low Side output FET.
It provides high current through a low impedance to turn on
33937
Analog Integrated Circuit Device Data
Freescale Semiconductor
24
FREESCALE [ Freescale ]
