FUNCTIONAL INTERNAL BLOCK DESCRIPTION
the appropriate mask bit is set. The INT will be held in the
High state until the fault is removed, and the appropriate bit
in the Status Register 0 is cleared by the CLINT1 command.
This fault reporting mechanism is described in detail in the
Logic Commands and Registers section.
for VLS includes the charge pump and a linear regulator. The
regulation set point for the linear regulator is nominally at
15.34 V. As long as VLS output voltage (VLSOUT) is greater
than the VLS analog regulator threshold (VLSATH) minus
VTHREG, the charge pump is not active.
If VLSOUT < VLSATH – VTHREG the charge pump turns ON
until VLSOUT > VLSATH – VTHREG + VHYST
HOLD OFF CIRCUIT
The IC guarantees the output FETs are turned off in the
absence of VDD or VPWR by means of the Hold off circuit. A
small current source, generated from VSUP, typically
100 µA, is mirrored and pulls all the output gate drive pins low
when VDD is less than about 3.0 V, RST is active (low), or
when VLS is lower than the VLS_Disable threshold. A
minimum of approximately 3.0 V is required on VSUP to
energize the Hold off circuit.
VHYST is approximately 200 mV. VLSATH will not interfere
with this cycle even when there is overlap in the thresholds,
due to the design of the regulator system.
The maximum current the charge pump can supply is
dependent on the pump capacitor value and quality, the
pump frequency (nominally 130 kHz), and the Rdson of the
pump FETs. The effective charge voltage for the pump
capacitor would be VSYS – 2 * VDIODE. The total charge
transfer would then be CPUMP * (VSYS – 2*VDIODE).
Multiplying by the switch frequency gives the theoretical
CHARGE PUMP
current the pump can transfer: FPUMP * CPUMP * (VSYS
2*VDIODE).
–
The Charge Pump circuit provides the basic switching
elements required to implement a charge pump, when
combined with external capacitors and diodes for enhanced
low voltage operation.
NOTE: There is also another smaller, fully integrated
charge pump (Trickle Charge Pump - see Figure 2), which is
used to maintain the High Side drivers’ gate VGS in 100
percent duty cycle modes.
When the 33937 is connected per the typical application
using the charge pump (see Figure 22), the regulation path
33937
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
FREESCALE [ Freescale ]
