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33912 参数 Datasheet PDF下载

33912图片预览
型号: 33912
PDF下载: 下载PDF文件 查看货源
内容描述: LIN系统基础芯片,直流电动机预驱动器和电流 [LIN System Basis Chip with DC Motor Pre-driver and Current]
分类和应用: 驱动器
文件页数/大小: 47 页 / 596 K
品牌: FREESCALE [ Freescale ]
 浏览型号33912的Datasheet PDF文件第12页浏览型号33912的Datasheet PDF文件第13页浏览型号33912的Datasheet PDF文件第14页浏览型号33912的Datasheet PDF文件第15页浏览型号33912的Datasheet PDF文件第17页浏览型号33912的Datasheet PDF文件第18页浏览型号33912的Datasheet PDF文件第19页浏览型号33912的Datasheet PDF文件第20页  
ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
Table 4. Dynamic Electrical Characteristics (continued)  
Characteristics noted under conditions 5.5V VSUP 18V, -40°C TA 125°C for the 33912 and -40°C TA 85°C for the  
34912, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal  
conditions, unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
V/µs  
µs  
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE  
LIN Fast Slew Rate (Programming Mode)  
SR  
20  
FAST  
LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS(49)  
Propagation Delay and Symmetry(50)  
tREC_PD  
Propagation Delay Receiver, tREC_PD=MAX (tREC_PDR, tREC_PDF  
Symmetry of Receiver Propagation Delay tREC_PDF - tREC_PDR  
)
3.0  
6.0  
2.0  
tREC_SYM  
-2.0  
Bus Wake-Up Deglitcher (Sleep and Stop Modes)(51)  
tPROPWL  
42  
70  
95  
µs  
µs  
Bus Wake-Up Event Reported  
From Sleep Mode(52)  
tWAKE  
tWAKE  
1500  
17  
From Stop Mode(53)  
9.0  
13  
TXD Permanent Dominant State Delay  
tTXDDOM  
0.65  
1.0  
1.35  
s
PULSE WIDTH MODULATION INPUT PIN (PWMIN)  
PWMIN pin(54)  
fPWMIN  
kHz  
Max. frequency to drive HS and LS output pins  
10  
Notes  
49. VSUP from 7.0V to 18V, bus load RBUS and CBUS 1.0nF / 1.0k, 6.8nF / 660, 10nF / 500. Measurement thresholds: 50% of TXD  
signal to LIN signal threshold defined at each parameter. See Figure 6, page 18.  
50. See Figure 9, page 19  
51. See Figure 10, page 19 for Sleep and Figure 11, page 19 for Stop Mode.  
52. The measurement is done with 1µF capacitor and 0mA current load on VDD. The value takes into account the delay to charge the  
capacitor. The delay is measured between the bus wake-up threshold (VBUSWU) rising edge of the LIN bus and when V reaches 3.0V.  
DD  
See Figure 10, page 19. The delay depends of the load and capacitor on VDD  
.
53. In Stop Mode, the delay is measured between the bus wake-up threshold (VBUSWU) and the falling edge of the IRQ pin. See Figure 11,  
page 19.  
54. This parameter is guaranteed by process monitoring but not production tested.  
33912  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
16  
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