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33912 参数 Datasheet PDF下载

33912图片预览
型号: 33912
PDF下载: 下载PDF文件 查看货源
内容描述: LIN系统基础芯片,直流电动机预驱动器和电流 [LIN System Basis Chip with DC Motor Pre-driver and Current]
分类和应用: 驱动器
文件页数/大小: 47 页 / 596 K
品牌: FREESCALE [ Freescale ]
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ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
Table 4. Dynamic Electrical Characteristics  
Characteristics noted under conditions 5.5V VSUP 18V, -40°C TA 125°C for the 33912 and -40°C TA 85°C for the  
34912, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal  
conditions, unless otherwise noted.  
Characteristic  
SPI INTERFACE TIMING (SEE Figure 13, PAGE 20)  
SPI Operating Frequency  
Symbol  
Min  
Typ  
Max  
Unit  
f
t
4.0  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
MHz  
ns  
SPIOP  
SCLK Clock Period  
250  
110  
110  
100  
100  
40  
CLK  
PS  
SCLK Clock High Time(41)  
t
ns  
SCLKH  
W
SCLK Clock Low Time(41)  
t
ns  
SCLKL  
W
Falling Edge of CS to Rising Edge of SCLK(41)  
Falling Edge of SCLK to CS Rising Edge(41)  
MOSI to Falling Edge of SCLK(41)  
Falling Edge of SCLK to MOSI(41)  
MISO Rise Time(41)  
t
ns  
LEAD  
tLAG  
ns  
t
ns  
SISU  
t
40  
ns  
SIH  
tRSO  
ns  
C = 220pF  
L
40  
40  
MISO Fall Time(41)  
t
ns  
ns  
FSO  
C = 220pF  
L
Time from Falling or Rising Edges of CS to:(41)  
- MISO Low-impedance  
t
0.0  
0.0  
50  
50  
SOEN  
- MISO High-impedance  
t
SODIS  
Time from Rising Edge of SCLK to MISO Data Valid(41)  
t
ns  
VALID  
0.2 x VDD MISO 0.8 x VDD, CL = 100pF  
0.0  
75  
RST OUTPUT PIN  
Reset Low-level Duration After VDD High (see Figure 12, page 20)  
Reset Deglitch Filter Time  
t
0.65  
350  
1.0  
1.35  
900  
ms  
ns  
RST  
t
600  
RSTDF  
WINDOW WATCHDOG CONFIGURATION PIN (WDCONF)  
Watchdog Time Period(42)  
t
ms  
PWD  
External Resistor REXT = 20k(1%)  
External Resistor REXT = 200k(1%)  
Without External Resistor REXT (WDCONF Pin Open)  
8.5  
79  
10  
94  
11.5  
108  
205  
110  
150  
CURRENT SENSE AMPLIFIER(41)  
Common Mode Rejection Ratio  
Supply Voltage Rejection Ratio(43)  
Gain Bandwidth Product  
Output Slew-Rate  
CMR  
SVR  
GBP  
SR  
70  
60  
dB  
dB  
0.75  
0.5  
3.0  
MHz  
V/µs  
Notes  
41. This parameter is guaranteed by process monitoring but not production tested.  
42. Watchdog timing period calculation formula: tPWD [ms] = 0.466 * (REXT - 20) + 10 (REXT in kΩ)  
43. Analog Outputs are supplied by VDD  
33912  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
14  
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