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33910_10 参数 Datasheet PDF下载

33910_10图片预览
型号: 33910_10
PDF下载: 下载PDF文件 查看货源
内容描述: LIN系统基础芯片,高 [LIN System Basis Chip with High]
分类和应用:
文件页数/大小: 90 页 / 1134 K
品牌: FREESCALE [ Freescale ]
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MC33910BAC / MC34910BAC  
ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
Table 34. Dynamic Electrical Characteristics (continued)  
Characteristics noted under conditions 5.5 V VSUP 18 V, -40°C TA 125°C for the 33910 and -40°C TA 85°C for the  
34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal  
conditions, unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
L1 INPUT  
Wake-up Filter Time  
STATE MACHINE TIMING  
t
8.0  
20  
38  
μs  
WUF  
Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command)  
and Stop Mode Activation(107)  
tSTOP  
μs  
5.0  
Normal Request Mode Timeout (see Figure 33)  
t
110  
150  
205  
ms  
NRTOUT  
Delay Between SPI Command and HS Turn On(108)  
9.0 V < VSUP < 27 V  
tS-  
μs  
ON  
10  
10  
10  
Delay Between SPI Command and HS Turn Off(108)  
9.0 V < VSUP < 27 V  
tS-OFF  
μs  
Delay Between Normal Request and Normal Mode After a Watchdog Trigger  
Command (Normal Request mode)(107)  
tSNR2N  
μs  
μs  
Delay Between CS Wake-up (CS LOW to HIGH) in Stop Mode and:  
Normal Request mode, VDD ON and RST HIGH  
First Accepted SPI Command  
tWUCS  
tWUSPI  
9.0  
90  
15  
80  
N/A  
Minimum Time Between Rising and Falling Edge on the CS  
t2CS  
4.0  
μs  
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC(109), (110)  
Duty Cycle 1: D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 µs  
D1  
7.0 V VSUP 18 V  
0.396  
Duty Cycle 2: D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 µs  
D2  
7.6 V VSUP 18 V  
0.581  
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4 KBIT/SEC(109),(111)  
Duty Cycle 3: D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 µs  
D3  
μs  
μs  
7.0 V VSUP 18 V  
0.417  
Duty Cycle 4: D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 µs  
D4  
7.6 V VSUP 18 V  
0.590  
Notes  
107. This parameter is guaranteed by process monitoring but, not production tested.  
108. Delay between turn on or off command (rising edge on CS) and HS ON or OFF, excluding rise or fall time due to external load.  
109. Bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD signal to LIN signal  
threshold defined at each parameter. See Figure 27.  
110. See Figure 28.  
111. See Figure 29.  
33910  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
60  
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