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33910_10 参数 Datasheet PDF下载

33910_10图片预览
型号: 33910_10
PDF下载: 下载PDF文件 查看货源
内容描述: LIN系统基础芯片,高 [LIN System Basis Chip with High]
分类和应用:
文件页数/大小: 90 页 / 1134 K
品牌: FREESCALE [ Freescale ]
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MC33910BAC / MC34910BAC  
ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
Table 34. Dynamic Electrical Characteristics (continued)  
Characteristics noted under conditions 5.5 V VSUP 18 V, -40°C TA 125°C for the 33910 and -40°C TA 85°C for the  
34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal  
conditions, unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
V/μs  
μs  
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE  
LIN Fast Slew Rate (Programming mode)  
SR  
20  
FAST  
LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS(112)  
Propagation Delay and Symmetry(113)  
tREC_PD  
Propagation Delay Receiver, tREC_PD=max (tREC_PDR, tREC_PDF  
Symmetry of Receiver Propagation Delay tREC_PDF - tREC_PDR  
)
3.0  
6.0  
2.0  
tREC_SYM  
-2.0  
Bus Wake-up Deglitcher (Sleep and Stop modes)(114)  
tPROPWL  
42  
70  
95  
μs  
μs  
Bus Wake-up Event Reported  
From Sleep mode(115)  
From Stop mode(116)  
tWAKE  
tWAKE  
1500  
17  
9.0  
13  
TXD Permanent Dominant State Delay  
tTXDDOM  
0.65  
1.0  
1.35  
s
PULSE WIDTH MODULATION INPUT PIN (PWMIN)  
PWMIN pin(117)  
fPWMIN  
kHz  
Max. frequency to drive HS output pins  
10  
Notes  
112. VSUP from 7.0 V to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD  
signal to LIN signal threshold defined at each parameter. See Figure 6.  
113. See Figure 9.  
114. See Figure 10, for Sleep and Figure 11, for Stop mode.  
115. The measurement is done with 1.0 µF capacitor and 0 mA current load on VDD. The value takes into account the delay to charge the  
capacitor. The delay is measured between the bus wake-up threshold (VBUSWU) rising edge of the LIN bus and when V reaches 3.0 V.  
DD  
See Figure 10. The delay depends of the load and capacitor on VDD  
.
116. In Stop mode, the delay is measured between the bus wake-up threshold (VBUSWU) and the falling edge of the IRQ pin. See Figure 11.  
117. This parameter is guaranteed by process monitoring but, not production tested.  
33910  
Analog Integrated Circuit Device Data  
61  
Freescale Semiconductor  
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