TYPICAL APPLICATIONS
Missing watchdog refresh
VDD
Watchdog refresh
Watchdog
refresh
SPI (CS)
WD
RST
350 ms
INT
SBC in Normal request
& reset modes
SBC in Normal
mode
SBC in Normal
request & reset
modes
SBC in
RESET
mode
Reset each 350 ms
Figure 33. Power up sequence, No W/D write at first
POWER UP AND VDD GOING LOW WITH STOP MODE AS DEFAULT LOW POWER MODE IS SELECTED
The first part of Figure 34 is identical to Figure 33. If VDD is pulled below VDD undervoltage reset (typ 4.6 V), say by an
overcurrent or short circuit (for instance, short to 4.0 V), and if a low power mode previously selected was Stop mode, the 33742
enters Reset mode (RST pin is active). The WDOG pin stays HIGH, but the high level (Voh) follows V1 level. The INT pin goes
LOW.
When the VDD overload condition is removed, the 33742 restarts in Normal Request mode.
Under voltage at VDD
(VDD < VRSTTH)
VDD
Watchdog refresh
SPI (CS)
350 ms
WD
RST
INT
SBC in Normal request
& reset modes
SBC in Normal
mode
SBC in Reset
mode
SBC in
RESET
mode
Reset each 350 ms
Figure 34. Undervoltage on VDD
33742
Analog Integrated Circuit Device Data
Freescale Semiconductor
54
FREESCALE [ Freescale ]
