33291 参数 Datasheet PDF下载

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions 4.5 V

≤

V

DD

≤

5.5 V, 9.0 V

≤

V

PWR

≤

16 V, -40°C

≤

T

A

≤

125°C, unless otherwise noted.

Typical values noted reflect the approximate value with V

BAT

= 13 V, T

A

= 25°C.

Characteristic

Output OFF Open Load Detect Current

(21)

Output Programmed OFF, V

OUT

= 0.6 V

DD

Output Clamp Voltage

2.0 mA < I

OUT

< 200 mA

Output Leakage Current (V

DD

< 2.0 V)

Overtemperature Shutdown (Outputs OFF)

(23)

Overtemperature Shutdown Hysteresis

(23)

DIGITAL INTERFACE

Input Logic High Voltage

Input Logic Low Voltage

Input Logic Threshold Hysteresis (SCLK,

RST

, and SFPD)

SI Pull-Up Current (SI = 0 V)

CS

Pull-Up Current (

CS

= 0 V)

Symbol

I

OCO

Min

Typ

Max

Unit

µ

A

30

50

100

V

45

53

0

180

10

65

25

–

20

V

OK

I

OUT(LKG)

T

LIM

T

LIM(HYS)

-25

155

–

µ

A

°

C

°

C

V

IH

V

IL

V

I (HYS)

I

SI

I

CS

I

SCLK

I

RST

I

SFPD

V

SOH

V

SOL

I

SOT

C

IN

C

SOT

0.7

0

50

0

0

0

5.0

5.0

–

–

100

10

10

10

25

10

1.0

0.2

500

20

20

20

50

25

–

0.4

10

12

20

V

DD

V

DD

mV

µ

A

µ

A

µ

A

µ

A

µ

A

V

V

SCLK Pull-Down Current (SCLK = 5.0 V)

RST

Pull-Down Current (

RST

= 5.0 V)

SFPD Pull-Down Current (SFPD = 5.0 V)

SO High-State Output Voltage (I

OH

= 1.0 mA)

SO Low-State Output Voltage (I

OL

= -1.6 mA)

SO Tri-State Leakage Current (

CS

= 0.7 VDD, 0 V < V

SO

< V

DD

)

Input Capacitance (0 V < V

DD

< 5.5 V)

SO Tn-State Capacitance (0 V < V

DD

< 5.5 V)

V

DD

- 0.4 V V

DD

- 0.2 V

–

-10

–

–

0.2

0

–

–

µ

A

pF

pF

Notes

21. Output OFF Open Load Detect Current is the current required to flow through the load for the purpose of detecting the existence of an

open load condition when the specific output is commanded to be OFF.

22. Output leakage current measured with the output OFF and at 16 V.

23. This parameter is guaranteed by design, but it is not production tested.

24. Upper and lower logic threshold voltage levels apply to SI,

CS

, SCLK,

RST

, and SFPD inputs.

25. Hysteresis is characterized, but it is not production tested.

26. Input capacitance of SI

CS

, SCLK,

RST

, and SFPD for 0 V < V

DD

< 5.5 V. This parameter is guaranteed by design, but it is not production

tested.

27. Tri-state capacitance of SO for 0 V < V

DD

< 5.5 V. This parameter is guaranteed by design, but it is not production tested.

33291

Analog Integrated Circuit Device Data

Freescale Semiconductor

7