ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
tR (SI)
tF (SI)
< 50 ns
< 50 ns
0.2 V
V
= 5.0 V
V
= 14 V
DD
PWR
5.0 V
0.7 V
DD
50%
SCLK
DD
0
R = 26 Ω
L
V
t
OH
DLY(LH)
0.7 V
DD
33291
Under
Test
CS
Output
0.2 V
SO
(Low-to-High)
DD
V
V
OL
tR (SO)
tF (SO)
C
L
t
VALID
SO
OH
0.7 V
(High-to-Low)
DD
0.2 V
DD
V
t
OL
DLY(HL)
SO (Low-to-High) is for an output with internal conditions such that
the low-to-high transition of CS causes the SO output to switch from
high to low.
C represents the total capacitance of the test fixture and probe.
L
Figure 9. Switching Time Test Circuit
Figure 7. Valid Data Delay Time and
Valid Time Waveforms
V
= 5.0 V
V
= 11 V
DD
PWR
t
t
R(SI)
F(SI)
< 50 ns
< 50 ns
CS
SO
5.0 V
0
90%
Ι
= 2.0 Α
V
L
0.7 DD
10%
(Ουτπυτ ΟΝ)
0.2 V
DD
33291
Under
Output
CS
t
t
t
SO(DIS)
SO(EN)
Test
VTri-State
10%
SO(DIS)
C = 20 pF
L
90%
(High-to-Low)
t
SO(DIS)
t
SO(EN)
VOH
90%
SO
C represents the total capacitance of the test fixture and probe.
L
10%
(Low-to-High)
VTri-State
Figure 10. Output Fault Unlatch Disable
Delay Test Circuit
1. SO (high-to-low) waveform is for SO output with internal conditions such
that SO output is low except when an output is disabled as a result of de-
tecting a circuit fault with CS in a High Logic state; e.g., open load.
2. SO (low-to-high) waveform is for SO output with internal conditions such
that SO output is high except when an output is disabled as a result of de-
tecting a circuit fault with CS in a High Logic state; e.g., shortened load.
Figure 8. Enable and Disable Time Waveforms
33291
Analog Integrated Circuit Device Data
Freescale Semiconductor
10
FREESCALE [ Freescale ]
