ELECTRICAL CHARACTERISTICS
TIMING DIAGRAM
TIMING DIAGRAM
VIH
VIL
VIH
RST
0.2 VDD
tW(RST)
CS
0.2 VDD
VIL
tW(SCLKH
)
tLEAD
0.7 VDD
tR
tLAG
VIH
VIL
SCLK
SI
0.2 VDD
tSI(SU)
tW(SCLKL)
tSI(HOLD)
tF
0.7 VDD
VIH
VIL
Don't Care
Valid
Don't Care
Valid
Don't Care
0.2 VDD
Figure 4. Input Timing Switch Characteristics
ELECTRICAL PERFORMANCE CURVES
V
= 5.0 V
DD
V
= 5.0 V
V
= 2.5 V
Pull-Up
DD
R = 1.0 kΩ
L
33291
Under
Test
33291
Under
Test
SCLK
SO
SO
CS
C
= 200 pF
C
= 20 pF
L
L
CL represents the total capacitance of the test fixture and probe.
C represents the total capacitance of the test fixture and probe.
L
Figure 5. Valid Data Delay Time and
Valid Time Test Circuit
Figure 6. Enable and Disable Time Test Circuit
33291
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
FREESCALE [ Freescale ]
