ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.5 V
≤
V
DD
≤
5.5 V, 9.0 V
≤
V
PWR
≤
16 V, -40°C
≤
T
A
≤
125°C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at T
A
= 25°C under nominal conditions, unless otherwise noted.
Characteristic
POWER OUTPUT TIMING
Output Rise Time (V
PWR
= 13 V, R
L
= 26
Ω)
(28)
Output Fall Time (V
PWR
= 13 V, R
L
= 26
Ω)
(28)
Output Turn-ON Delay Time (V
PWR
= 13 V, R
L
= 26
Ω)
(29)
Output Turn-OFF Delay Time (V
PWR
= 13 V, R
L
= 26
Ω)
(30)
Output Short Fault Disable Report Delay
(31)
SFPD = 0.2 x V
DD
Output OFF Fault Report Delay
(32)
SFPD = 0.2 x V
DD
DIGITAL INTERFACE TIMING
Required Low State Duration for
RST
(V
IL
< 0.2 V
DD
)
(32)
Falling Edge of
CS
to Rising Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to Rising Edge of
CS
(Required for Setup Time)
SI to Falling Edge of SCLK (Required for Setup Time)
Falling Edge of SCLK to SI (Required for Hold Time)
SO Rise Time (C
L
= 200 pF)
SO Fall Time (C
L
= 200 pF)
SI,
CS
, SCLK, Incoming Signal Rise Time
(34)
SI,
CS
, SCLK, Incoming Signal Fall Time
(34)
Time from Falling Edge of
CS
to SO Low Impedance
(35)
Time from Rising Edge of
CS
to SO High Impedance
(36)
Time from Rising Edge of SCLK to SO Data Valid
(37)
0.2 V
DD
≤
SO
≥
0.8 V
DD
, C
L
= 200 pF
t
W(RST)
t
LEAD
t
LAG
t
SI (SU)
t
SI (HOLD)
t
R (SO)
t
F (SO)
t
R (SI)
t
F (SI)
t
SO(EN)
t
SO(DIS)
t
VALID
–
65
105
–
–
–
–
–
–
–
–
–
–
–
50
50
50
25
25
25
25
–
–
–
–
167
167
167
83
83
50
50
50
50
110
110
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
DLY (OFF)
70
150
250
t
R
t
F
t
DLY (ON)
t
DLY (OFF)
t
DLY (SF)
70
150
250
0.4
0.4
1.0
1.0
5.0
5.0
15
15
20
20
50
50
Symbol
Min
Typ
Max
Unit
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
Notes
28. Output Rise and Fall time respectively measured across a 26
Ω
resistive load at 10% to 90% and 90% to 10% voltage points.
29. Output Turn-ON Delay time measured from 50% rising edge of
CS
to 90% of Output OFF voltage (V
PWR
) with R
L
= 26
Ω
resistive load.
30.
31.
32.
33.
34.
35.
36.
37.
Output Turn-OFF Delay time measured from 50% rising edge of
CS
to 10% of Output OFF voltage (V
PWR
) with R
L
= 26
Ω
resistive load.
Propagation time of Short Fault Disable Report measured from 50% rising edge of
CS
to 10% Output OFF voltage (V
PWR
), V
PWR
=
6.0 V and SFPD = 2.0 x V
DD
.
Output OFF Fault Report Delay measured from 50% rising edge of
CS
to 10% rising edge of Output OFF voltage (V
PWR
).
RST
Low duration measured with outputs enabled and going to OFF or disabled condition.
Rise and Fall time of incoming SI,
CS
, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at the SO pin.
Time required for output status data to be terminated at the SO pin.
Time required to obtain valid data out from SO following the rise of SCLK. See
33291
8
Analog Integrated Circuit Device Data
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
