Clocking
Table 60. CSB Frequency Options for Agent Mode (continued)
Input Clock Frequency (MHz)2
CFG_CLKIN_DIV
at Reset1
csb_clk :
SPMF
16.67
25
33.33
66.67
Input Clock Ratio2
csb_clk Frequency (MHz)
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
High
High
High
High
High
High
High
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0010
0011
0100
0101
0110
0111
1000
6 : 1
7 : 1
100
150
175
200
225
250
275
300
325
200
233
266
300
333
116
133
150
166
183
200
216
8 : 1
9 : 1
10 : 1
11 : 1
12 : 1
13 : 1
14 : 1
15 : 1
16 : 1
4 : 1
233
250
266
100
150
200
250
300
133
200
266
333
266
6 : 1
100
133
166
200
233
266
8 : 1
10 : 1
12 : 1
14 : 1
16 : 1
1
2
CFG_CLKIN_DIV doubles csb_clk if set high.
CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
19.2 Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). Table 61 shows the encodings for RCWL[COREPLL]. COREPLL values that are
not listed in Table 61 should be considered as reserved.
NOTE
Core VCO frequency = core frequency × VCO divider
VCO divider must be set properly so that the core VCO frequency is in the
range of 800–1800 MHz.
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
Freescale Semiconductor
71
FREESCALE [ Freescale ]
