Clocking
Table 58. System PLL Multiplication Factors (continued)
RCWL[SPMF]
System PLL Multiplication Factor
0111
1000
1001
1010
1011
1100
1101
1110
1111
× 7
× 8
× 9
× 10
× 11
× 12
× 13
× 14
× 15
As described in Section 19, “Clocking,” the LBIUCM, DDRCM, and SPMF parameters in the reset
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 59
and Table 60 show the expected frequency values for the CSB frequency for select csb_clk to
CLKIN/PCI_SYNC_IN ratios.
Table 59. CSB Frequency Options for Host Mode
Input Clock Frequency (MHz)2
CFG_CLKIN_DIV
at Reset1
csb_clk :
SPMF
16.67
25
33.33
66.67
Input Clock Ratio2
csb_clk Frequency (MHz)
Low
Low
Low
Low
0010
0011
0100
0101
2 : 1
3 : 1
4 : 1
5 : 1
133
200
266
333
100
100
125
133
166
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
Freescale Semiconductor
69
FREESCALE [ Freescale ]
