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1500457 参数 Datasheet PDF下载

1500457图片预览
型号: 1500457
PDF下载: 下载PDF文件 查看货源
内容描述: 综合主机处理器的硬件规格 [Integrated Host Processor Hardware Specifications]
分类和应用:
文件页数/大小: 87 页 / 680 K
品牌: FREESCALE [ Freescale ]
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Clocking  
Table 57 provides the operating frequencies for the MPC8349EA TBGA under recommended operating  
conditions (see Table 2).  
Table 57. Operating Frequencies for TBGA  
Characteristic1  
e300 core frequency (core_clk)  
400 MHz  
533 MHz  
667 MHz  
Unit  
266–400  
100–266  
100–133  
100–133  
16.67–133  
25–66  
266–533  
100–333  
100–133  
100–133  
16.67–133  
25–66  
266–667  
100–333  
100–166.67  
100–200  
16.67–133  
25–66  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
Coherent system bus frequency (csb_clk)  
DDR1 memory bus frequency (MCK)2  
DDR2 memory bus frequency (MCK)3  
Local bus frequency (LCLKn)4  
PCI input frequency (CLKIN or PCI_CLK)  
Security core maximum internal operating frequency  
USB_DR, USB_MPH maximum internal operating frequency  
133  
133  
166  
133  
133  
166  
1
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCK,  
LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value of  
SCCR[ENCCM], SCCR[USBDRCM] and SCCR[USBMPHCM] must be programmed so that the maximum internal operating  
frequency of the security core and USB modules does not exceed the respective values listed in this table.  
The DDR data rate is 2x the DDR memory bus frequency.  
The DDR data rate is 2x the DDR memory bus frequency.  
The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x the  
csb_clk frequency (depending on RCWL[LBIUCM]).  
2
3
4
All frequency combinations shown in the table below may not be available. Maximum operating  
frequencies depend on the part ordered, see Section 22.1, “Part Numbers Fully Addressed by This  
Document,” for part ordering details and contact your Freescale Sales Representative or authorized  
distributor for more information.  
19.1  
System PLL Configuration  
The system PLL is controlled by the RCWL[SPMF] parameter. Table 58 shows the multiplication factor  
encodings for the system PLL.  
Table 58. System PLL Multiplication Factors  
RCWL[SPMF]  
System PLL Multiplication Factor  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
× 16  
Reserved  
× 2  
× 3  
× 4  
× 5  
× 6  
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13  
Freescale Semiconductor  
68