F81867
This bit works only in 9-bit mode.
0: the SM2 bit will be cleared by host, so that data could be received.
6
AUTO_ADDR
R/W LRESET#
0
1: the SM2 bit will be cleared by hardware according to the sent address and
the given address (or broadcast address derived by SADDR and SADEN)
5
4
RS485_INV
RS485_EN
Reserved
R/W LRESET#
R/W LRESET#
0
0
-
Invert RTS# if RS485_EN is set.
0: RS232 driver.
1: RS485 driver. RTS# is driven high automatically when transmitting
data, otherwise is kept low.
3-2
-
LRESET#
Reserved.
IRQ_MODE1 and IRQ_MODE0 will select the UART5 interrupt mode if IRQ
sharing is enabled.
00 : Sharing IRQ active low Level mode.
01 : Sharing IRQ active high edge mode.
10 : Sharing IRQ active high Level mode.
1
0
IRQ_MODE0
IRQ_SHARE
R/W LRESET#
0
0
11 : Reserved.
This bit is effective at IRQ is sharing with the other device (IRQ_SHARE, bit 1).
0 : IRQ is not sharing with other device.
1 : IRQ is sharing with other device.
R/W LRESET#
Clock Register ⎯ Index F2h
Bit
Name
R/W Reset Default
Description
7-2
Reserved
-
-
-
Reserved.
Select the clock source for UART5.
00: 1.8432MHz.
1-0
UART5_CLK_SEL R/W LRESET# 00b 01: 18.432MHz.
10: 24MHz.
11: 14.769MHz.
9bit-mode Slave Address Register ⎯ Index F4h
Bit
Name
R/W Reset Default
Description
This byte accompanying with SADEN will determine the given address and
broadcast address in 9-bit mode. The UART will response to both given and
broadcast address.
Following description determines the given address and broadcast address:
17. given address: If bit n of SADEN is “0”, then the corresponding bit of
SADDR is don’t care.
18. broadcast address: If bit n of ORed SADDR and SADEN is “0”, don’t care
that bit. The remaining bit which is “1” is compared to the received
address.
7-0
SADDR
R/W LRESET#
00h
Ex.
SADDR
SADEN
0101_1100b
1111_1001b
0101_1xx0b
1111_11x1b
Given Address
Broadcast Address
202
Dec, 2011
V0.12P