F81867
Base Address High Register ⎯ Index 60h
Bit
Name
R/W Reset Default
R/W 5VSB 00h The MSB of H2E base address.
Description
Description
Description
7-0
BASE_ADDR_HI
Base Address Low Register ⎯ Index 61h
Bit
Name
R/W Reset Default
R/W 5VSB 00h The LSB of H2E base address.
7-0
BASE_ADDR_LO
IRQ Channel Select Register ⎯ Index 70h
Bit
7-4
3-0
Name
R/W Reset Default
Reserved
SELH2EIRQ
-
-
-
Reserved.
R/W 5VSB
00h Select the IRQ channel for H2E.
7.13 Debug Port Host Side Registers (LDN 0x0F)
Default Value
Register
0x[HEX]
Register Name
MSB
LSB
30
60
61
Debug Port I/O Port Enable Register
Base Address High Register
Base Address Low Register
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Debug Port I/O Port Enable Register ⎯ Index 30h
Bit
Name
R/W Reset Default
Description
7-1
Reserved
-
-
-
Reserved
0: disable Debug Port I/O port.
1: enable Debug Port I/O port.
0
DBPORT_IO_EN
R/W 5VSB
0
Base Address High Register ⎯ Index 60h
Bit
Name
R/W Reset Default
Description
7-0
BASE_ADDR_HI
R/W 5VSB 00h The MSB of Debug Port base address.
Base Address Low Register ⎯ Index 61h
Bit
Name
R/W Reset Default
R/W 5VSB
Description
Description
7-0
BASE_ADDR_LO
00h The LSB of Debug Port base address.
Debug Port Read Data Register ⎯ Offset + 0x00
Bit
Name
R/W Reset Default
5VSB
7-0
DBPORT_DATA
R
00h The reading of μC side register from the debug port.
Debug Port Control Register ⎯ Offset + 0x01
Bit
Name
R/W Reset Default
Description
7
BRK_PRT_TRIG
R
-
0
Status of breakpoint trigger.
188
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
