F81867
RI De-bounce Select Register ⎯ Index FEh
Bit
Name
R/W
Default
Description
Reset
7-2
Reserved
-
-
-
Reserved
Select RI# de-bounce time.
00: reserved.
01: 200us.
1-0
RI_DB_SEL
R/W 5VSB
0
10: 2ms.
11: 20ms.
ERP Enable Register ⎯ Index E0h
Bit
Name
R/W
Default
Description
Reset
0 : disable ERP function
1: enable ERP function
7
ERP_EN
R/W VBAT
R/W VBAT
0
This bit will set “1” when system is back from S3 state.
Reserved
6
S3_BACK
Reserved
0
-
5-2
-
-
RING1 PME event enable.
1
0
RING_PME_EN
R/W VBAT
R/W VBAT
0
0
0: disable RING1 PME event.
1: enable RING1 PME event, when RING1 falling edge detect
RING1 PWSOUT event enable.
RING_PWSOUT_EN
0: disable RING1 PWSOUT event.
1: enable RING1 PWSOUT event, when RING1 falling edge detect
ERP Control Register 1 ⎯ Index E1h
Bit
Name
R/W
Default
Description
Reset
Reserved
7-6
Reserved
-
-
-
If clear to “0” ERP_CTRL1# will output Low when S3 state. Else If set
to “1” ERP_CTRL1# will output High when S3 state.
5
4
3
2
1
0
S3_ ERP_CTRL1#_DIS
R/W VBAT
0
0
1
1
0
0
If clear to “0” ERP_CTRL0# will output Low when S3 state. Else If set
to “1” ERP_CTRL0# will output High when S3 state.
S3 _ ERP_CTRL0#_DIS R/W VBAT
S5 _ ERP_CTRL1#_DIS R/W VBAT
S5 _ ERP_CTRL0#_DIS R/W VBAT
AC_ ERP_CTRL1#_DIS R/W VBAT
AC_ ERP_CTRL0#_DIS R/W VBAT
If clear to “0” ERP_CTRL1# will output Low when S5 state. Else If set
to “1” ERP_CTRL1# will output High when S5 state.
If clear to “0” ERP_CTRL0# will output Low when S5 state. Else If set
to “1” ERP_CTRL0# will output High when S5 state.
If clear to “0” ERP_CTRL1# will output Low when after AC lost. Else If
set to “1” ERP_CTRL1# will output High when after AC lost.
If clear to “0” ERP_CTRL0# will output Low when after AC lost. Else If
set to “1” ERP_CTRL0# will output High when after AC lost.
ERP Control Register 2 ⎯ Index E2h
Bit
Name
R/W
Default
Description
Reset
7
6
AC_LOST
Reserved
R
5VSB
1
0
This bit is AC lost status and writes 1 to this bit will clear it.
Reserved
R/W VBAT
184
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
