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F81867D 参数 Datasheet PDF下载

F81867D图片预览
型号: F81867D
PDF下载: 下载PDF文件 查看货源
内容描述: 6个UART μSuper IO 128字节FIFO和省电功能 [6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions]
分类和应用: 先进先出芯片
文件页数/大小: 315 页 / 2394 K
品牌: FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
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F81867  
ERP Deep S3 Delay Register Index E9h  
Bit  
Name  
R/W  
Default  
Description  
Reset  
The delay time from S3 state to deep S3 state. The unit is 64ms and  
default is 1.024 sec.  
7-0  
DS3_DELAY_TIME  
R/W VBAT  
Fh  
ERP Mode Select Register Index ECh  
Bit  
Name  
R/W  
Default  
Description  
Reset  
00: Fintek G3’ mode.  
01: Intel DSW + Fintek G3` mode.  
10: Reserved.  
7-6  
ERP_MODE  
R/W VBAT  
0
11: Intel DSW mode.  
5
4
DPWROK_CTRL_EN  
SOFT_START_EN  
R/W VBAT  
R/W VBAT  
0
1
Set “1” to enable DPWROK reset by ERP_CTRL1#.  
0: disable ERP soft start.  
1: enable ERP soft start.  
The soft start rate.  
00: 5ms.  
3-2  
1-0  
SOFT_START_RATE  
Reserved  
R/W VBAT  
1h  
-
01: 10ms.  
10: 27ms.  
11: 54ms.  
-
-
Reserved  
ERP WDT Control Register Index EDh  
Bit  
Name  
R/W  
Default  
Description  
Reset  
Time of ERP watchdog timer.  
7-6  
ERP_WD_TIME[11:10]  
R/W  
-
VBAT  
Write index EEh will load watchdog time.  
7-5  
4
Reserved  
R
R
-
-
-
-
Reserved  
ERP_WDTMOUT_STATUS  
ERP_WD_TIME[9:8]  
VBAT  
Watchdog timeout status.  
Reserved  
3-2  
R/W VBAT  
R/W VBAT  
R/W VBAT  
ERP WDT unit. It is the time unit of ERP_WD_TIME.  
0: 1sec.  
1
0
WD_UNIT  
WD_EN  
0
0
1: 60 sec.  
Set “1” to enable ERP WDT. Auto clear if timeout occurred.  
ERP WDT Time Register Index EEh  
Reset  
Bit  
Name  
R/W  
Default  
Description  
7-0  
ERP_WD_TIME  
R/W VBAT  
0
Time of ERP watchdog timer.  
186  
Dec, 2011  
V0.12P  
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