F81867
6-1
0
Reserved
-
5VSB
-
Reserved
Set “!” to enable debug port. Debug port register could be accessed by set
address to 0x3200 + offset. To access the μC side register including SFR
and RAM data. Entry key should be entered via the debug port μC side
register.
DBPORT_EN
R/W 5VSB
0
Debug Port Control Register ⎯ Offset + 0x01
Bit
7
Name
R/W Reset Default
Description
BRK_PRT_TRIG
Reserved
R
-
5VSB
-
0
-
Status of breakpoint trigger.
Reserved
6-1
Set “!” to enable debug port. Debug port register could be accessed by set
address to 0x3200 + offset. To access the μC side register including SFR
and RAM data. Entry key should be entered via debug port μC side register.
0
DBPORT_EN
R/W 5VSB
0
Debug Port Address Low Byte Register ⎯ Offset + 0x04
Name R/W Reset Default
Bit
Description
7-0 DBPORT_L_ADDR R/W 5VSB
0
Address low byte for μC side register address.
Debug Port Address High Byte Register ⎯ Offset + 0x05
Name R/W Reset Default
7-0 DBPORT_H_ADDR R/W 5VSB
Bit
Description
0
Address high byte for μC side register address.
7.14 UART1 Registers (CR10)
“-“ Reserved or Tri-State
Default Value
Register 0x[HEX]
30
Register Name
MSB
LSB
Device Enable Register
-
-
0
1
-
-
0
1
-
-
0
1
-
-
0
1
0
-
-
0
0
1
-
-
1
1
0
0
0
0
0
0
0
60
61
70
F0
F2
F4
F5
F6
Base Address High Register
Base Address Low Register
IRQ Channel Select Register
IRQ Share Register
0
1
-
1
0
0
0
0
0
0
0
0
-
0
-
0
-
0
-
Clock Select Register
-
-
9bit-mode Slave Address Register
9bit-mode Slave Address Mask Register
FIFO Mode Register
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
UART 1 Device Enable Register ⎯ Index 30h
Bit
Name
R/W Reset Default
Description
7-1
Reserved
-
-
-
Reserved
0: disable UART 1 I/O Port.
1: enable UART 1 I/O Port.
0
UART 1_EN
R/W LRESET#
1
189
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
