F81867
2
Reserved
-
-
-
Reserved.
Select the FIFO depth.
00: 16-byte FIFO.
1-0
FIFO_MODE
R/W LRESET#
00h 01: 32-byte FIFO.
10: 64-byte FIFO.
11: 128-byte FIFO.
7.15 UART2 Registers (CR11)
“-“ Reserved or Tri-State
Register 0x[HEX]
Default Value
Register Name
Device Enable Register
MSB
LSB
30
60
61
F0
F2
F4
F5
F0
F6
-
-
0
1
-
-
0
1
-
-
0
1
-
-
0
1
0
-
-
0
0
0
-
-
1
0
0
1
0
0
0
0
0
Base Address High Register
Base Address Low Register
IRQ Share Register
0
1
-
1
0
1
0
0
0
0
0
Clock Select Register
0
-
0
-
0
-
0
-
9bit-mode Slave Address Register
9bit-mode Slave Address Mask Register
IRQ Share Register
-
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
FIFO Mode Register
UART 2 Device Enable Register ⎯ Index 30h
Bit
Name
R/W Reset Default
Description
7-1
Reserved
-
-
-
Reserved
0: disable UART 2 I/O Port.
1: enable UART 2 I/O Port.
0
UART2_EN
R/W LRESET#
1
Base Address High Register ⎯ Index 60h
Bit
Name
R/W Reset Default
Description
7-0
BASE_ADDR_HI
R/W LRESET#
02h The MSB of UART 2 base address.
Base Address Low Register ⎯ Index 61h
Bit
Name
R/W Reset Default
Description
Description
7-1
BASE_ADDR_LO
R/W LRESET#
F8h The LSB of UART 2 base address.
IRQ Channel Select Register ⎯ Index 70h
Bit
7-4
3-0
Name
R/W Reset Default
Reserved
-
-
-
Reserved.
Select the IRQ channel for UART 2.
SELUR12RQ
R/W LRESET#
3h
192
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
