F81867
The three bits {LED_VSB_S3_MODE_ADD, LED_VSB_S3_MODE [1:0]}
select the LED_VSB mode in S3 state.
000: Sink low.
001: Tri-state or drive high control by GPIO10_DRV_EN.
010: 0.5Hz clock with 50% duty.
011: 1Hz clock with 50% duty.
3-2
LED_VSB_S3_MODE R/W VBAT
00
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 25% duty.*
111: 0.25Hz clock with 25% duty.*
The three bits {LED_VSB_S0_MODE_ADD, LED_VSB_S0_MODE [1:0]}
select the LED_VSB mode in S0 state.
000: Sink low.
001: Tri-state or drive high control by GPIO10_DRV_EN.
010: 0.5Hz clock with 50% duty.
011: 1Hz clock with 50% duty.
1-0
LED_VSB_S0_MODE R/W VBAT
00
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 25% duty.*
111: 0.25Hz clock with 25% duty.*
DSW Delay Register ⎯ Index FCh
Bit
Name
R/W
Default
Description
EC to Host PME event status.
Reset
0: EC to Host has no PME event.
E2H_PME_ST
R/WC
-
7
-
1: EC to Host has a PME event to assert. Write 1 to clear to be ready
for next PME event.
CIR wakeup PME event status.
0: CIR wakeup has no PME event.
CIR_PME_ST
E2H_PME_EN
R/WC
-
-
6
5
5VSB
1: CIR wakeup a PME event to assert. Write 1 to clear to be ready for
next PME event.
EC to Host PME event enable.
0: Disable EC to Host PME event.
1: Enable EC to Host PME event.
CIR event enable.
R/WC
R/WC
-
CIR_PME_EN
DSW_DELAY
-
0: Disable CIR PME event.
1: Enable CIR PME event.
4
5VSB
This is the delay time between SUS_WARN# and SUS_ACK#. The
unit is 0.5 sec. Default time is 3.5s ~ 4s. The default could be trimmed
to 0s ~ 0.5s.
3-0
R/W 5VSB
7
183
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
