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F81866A 参数 Datasheet PDF下载

F81866A图片预览
型号: F81866A
PDF下载: 下载PDF文件 查看货源
内容描述: 6个UART超级IO 128字节FIFO和电源 [6 UARTs Super IO With 128 Bytes FIFO and Power]
分类和应用: 先进先出芯片
文件页数/大小: 210 页 / 1806 K
品牌: FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
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F81866A  
7.9.12DSW Delay Register Index FCh  
Bit  
Name  
R/W  
Default  
Description  
Reset  
7-4  
Reserved  
-
-
-
Reserved  
This is the delay time between SUS_WARN# and SUS_ACK#. The  
unit is 0.5 sec. Default time is 3.5s ~ 4s. The default could be trimmed  
to 0s ~ 0.5s.  
3-0  
DSW_DELAY  
R/W 5VSB  
7
7.9.13RI De-bounce Select Register Index FEh  
Bit  
Name  
R/W  
Default  
Description  
Reset  
7-2  
Reserved  
-
-
-
Reserved  
Select RI# de-bounce time.  
00: reserved.  
01: 200us.  
1-0  
RI_DB_SEL  
R/W 5VSB  
0
10: 2ms.  
11: 20ms.  
7.9.14ERP Enable Register Index E0h  
Bit  
Name  
R/W  
Default  
Description  
Reset  
0 : disable ERP function  
1: enable ERP function  
7
ERP_EN  
R/W VBAT  
R/W VBAT  
0
This bit will set “1” when system is back from S3 state.  
Reserved  
6
S3_BACK  
Reserved  
0
-
5-2  
-
-
RING1 PME event enable.  
1
0
RING_PME_EN  
R/W VBAT  
R/W VBAT  
0
0
0: disable RING1 PME event.  
1: enable RING1 PME event, when RING1 falling edge detect  
RING1 PWSOUT event enable.  
RING_PWSOUT_EN  
0: disable RING1 PWSOUT event.  
1: enable RING1 PWSOUT event, when RING1 falling edge detect  
7.9.15ERP Control Register 1 Index E1h  
Bit  
Name  
R/W  
Default  
Description  
Reset  
Reserved  
7-6  
Reserved  
-
-
-
If clear to “0” ERP_CTRL1# will output Low when S3 state. Else If set  
to “1” ERP_CTRL1# will output High when S3 state.  
5
4
3
2
1
0
S3_ ERP_CTRL1#_DIS  
R/W VBAT  
0
0
1
1
0
0
If clear to “0” ERP_CTRL0# will output Low when S3 state. Else If set  
to “1” ERP_CTRL0# will output High when S3 state.  
S3 _ ERP_CTRL0#_DIS R/W VBAT  
S5 _ ERP_CTRL1#_DIS R/W VBAT  
S5 _ ERP_CTRL0#_DIS R/W VBAT  
AC_ ERP_CTRL1#_DIS R/W VBAT  
AC_ ERP_CTRL0#_DIS R/W VBAT  
If clear to “0” ERP_CTRL1# will output Low when S5 state. Else If set  
to “1” ERP_CTRL1# will output High when S5 state.  
If clear to “0” ERP_CTRL0# will output Low when S5 state. Else If set  
to “1” ERP_CTRL0# will output High when S5 state.  
If clear to “0” ERP_CTRL1# will output Low when after AC lost. Else If  
set to “1” ERP_CTRL1# will output High when after AC lost.  
If clear to “0” ERP_CTRL0# will output Low when after AC lost. Else If  
set to “1” ERP_CTRL0# will output High when after AC lost.  
175  
Jan, 2012  
V0. 12P  
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