F81866A
7.9.26ERP WDT Time Register ⎯ Index EEh
Reset
Bit
Name
R/W
Default
Description
Time of ERP watchdog timer.
7-0
ERP_WD_TIME
R/W VBAT
0
7.10 UART1 Device Configuration Registers (LDN CR10)
“-“ Reserved or Tri-State
Register 0x[HEX]
Default Value
Register Name
Device Enable Register
MSB
LSB
30
60
61
70
F0
F2
F4
F5
F6
-
-
0
1
-
-
0
1
-
-
0
1
-
-
0
1
0
-
-
0
0
1
-
-
1
1
0
0
0
0
0
0
0
Base Address High Register
Base Address Low Register
IRQ Channel Select Register
IRQ Share Register
0
1
-
1
0
0
0
0
0
0
0
0
-
0
-
0
-
0
-
Clock Select Register
-
-
9bit-mode Slave Address Register
9bit-mode Slave Address Mask Register
FIFO Mode Register
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
7.10.1UART 1 Device Enable Register ⎯ Index 30h
Bit
Name
R/W Reset Default
Description
7-1
Reserved
-
-
-
Reserved
0: disable UART 1 I/O Port.
1: enable UART 1 I/O Port.
0
UART 1_EN
R/W LRESET#
1
7.10.2Base Address High Register ⎯ Index 60h
Bit
Name
R/W Reset Default
Description
7-0
BASE_ADDR_HI
R/W LRESET#
03h The MSB of UART 1 base address.
7.10.3Base Address Low Register ⎯ Index 61h
Bit
Name
R/W Reset Default
Description
Description
7-0
BASE_ADDR_LO
R/W LRESET#
F8h The LSB of UART 1 base address.
7.10.4IRQ Channel Select Register ⎯ Index 70h
Bit
7-4
3-0
Name
R/W Reset Default
Reserved
-
-
-
Reserved.
Select the IRQ channel for UART 1.
SELUR1IRQ
R/W LRESET#
4h
178
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
