F81866A
7.9.16ERP Control Register 2 ⎯ Index E2h
Bit
Name
R/W
Default
Description
Reset
7
6
AC_LOST
Reserved
R
5VSB
1
0
This bit is AC lost status and writes 1 to this bit will clear it.
Reserved
R/W VBAT
0: Disable ERP_CTRL1# assert RSMRST low
1: Enable ERP_CTRL1# assert RSMRST low
5
VSB_CTRL_EN[1]
R/W VBAT
1’b0
0: Disable ERP_CTRL0# assert RSMRST low
1: Enable ERP_CTRL0# assert RSMRST low
4
VSB_CTRL_EN[0]
Reserved
R/W VBAT
R/W VBAT
1’b0
0
3-2
Reserved
Device detects 5VSB power ok (4.4V) and VSB3V_IN become high,
and after ~50ms de-bounce time RSMRST will become high. But when
user set this bit to 1. RSMRST will not check 5VSB power ok.
1
0
RSMRST_DET_5V_N
Reserved
R/W VBAT
0
-
R
-
Reserved
7.9.17ERP PWSIN De-bounce Register ⎯ Index E3h
Reset
Bit
Name
R/W
Default
Description
7-0
PWSIN_DEB_TIME
R/W VBAT
13h PWSIN# pin input de-bounce time. The unit is 1ms, default is 20ms.
7.9.18ERP RSMRST De-bounce Register ⎯ Index E4h
Bit
Name
R/W
Default
Description
Reset
RSMRST internal de-bounce time. The unit is 1ms and default is
10ms.
7-0
RSMRST_DEB_TIME
R/W VBAT
9h
7.9.19ERP PWSOUT Pulse Width Register ⎯ Index E5h
Bit
Name
R/W
Default
Description
Reset
7-0
PWSOUT_PW
R/W VBAT
C7h PWSOUT output pulse width. The unit is 1ms and default is 200ms.
7.9.20ERP PWSIN De-bounce Register ⎯ Index E6h
Bit
Name
R/W
Default
Description
Reset
7-0
PSON_DEB_TIME
R/W VBAT
13h PSON# pin input de-bounce time. The unit is 1ms, default is 10ms.
7.9.21ERP Deep S5 Delay Register ⎯ Index E7h
Bit
Name
R/W
Default
Description
Reset
The delay time from S5 state to deep S5 state. The unit is 64ms and
default is 6.4 sec.
7-0
DS5_DELAY_TIME
R/W VBAT
63h
7.9.22ERP Wakeup Enable Register ⎯ Index E8h
Bit
Name
R/W
Default
Description
Reset
7
6
RI2_WAKEUP_EN
Reserved
R/W VBAT
0
-
Set this bit to enable RI2# event to wakeup system.
Reserved
-
-
176
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
