F81866A
UART 1 PME event enable.
0: disable UART 1 PME event.
1: enable UART 1 PME event.
0
UART1_PME_EN R/W 5VSB
0
7.9.5PME Event Status 2 Register ⎯ Index F3h
Bit
Name
R/W
Default
Description
Reset
RI2# PME event status.
0: RI2# has no PME event.
7
RI2_PME_ST
R/WC
-
5VSB
1: RI2# has a PME event to assert. Write 1 to clear to be ready for next PME
event.
RI1# PME event status.
0: RI1# has no PME event.
6
5
4
3
2
1
RI1_PME_ST
R/WC
-
-
-
-
-
-
5VSB
1: RI1# has a PME event to assert. Write 1 to clear to be ready for next PME
event.
UART 6 PME event status.
0: UART 6 has no PME event.
UART6_PME_ST R/WC 5VSB
UART5_PME_ST R/WC 5VSB
UART4_PME_ST R/WC 5VSB
UART3_PME_ST R/WC 5VSB
UART2_PME_ST R/WC 5VSB
1: UART 6 has a PME event to assert. Write 1 to clear to be ready for next
PME event.
UART 5 PME event status.
0: UART 5 has no PME event.
1: UART 5 has a PME event to assert. Write 1 to clear to be ready for next
PME event.
UART 4 PME event status.
0: UART 4 has no PME event.
1: UART 4 has a PME event to assert. Write 1 to clear to be ready for next
PME event.
UART 3 PME event status.
0: UART 3 has no PME event.
1: UART 3 has a PME event to assert. Write 1 to clear to be ready for next
PME event.
UART 2 PME event status.
0: UART 2 has no PME event.
1: UART 2 has a PME event to assert. Write 1 to clear to be ready for next
PME event.
171
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
