F81866A
7.1.1310Hz Clock Divisor High Byte ⎯ Index 29h (Powered by VBAT, available when CLK_ TUNE_PROG_EN
= 1)
Bit
Name
R/W Reset Default
Description
Write “1” to start the fine tune mechanism. The hardware will start to count
10 cycle internal 500KHz clock with 48MHz clock. The count will present in
index 0x2A, 0x2B.
7
FINE_TUNE_START
W
-
-
-
-
-
6-4
3-0
Reserved
Reserved.
The divisor of 10Hz clock. Internal 10Hz clock is used to generate WDT
event. It is divided from 10KHz clock and could be fine tune by change its
divisor.
CLK10HZ_DIV
R/W VBAT
4’h3
7.1.1410Hz Clock Divisor Low Byte ⎯ Index 2Ah (Available when CLK_ TUNE_PROG_EN = 0)
Bit
Name
R/W Reset Default
R/W
Description
7-0
Reserved
-
0
Reserved.
7.1.1510Hz Clock Divisor Low Byte ⎯ Index 2Ah (Available when CLK_TUNE_PROG_EN = 1)
Bit
Name
R/W Reset Default
Description
The divisor of 10Hz clock. Internal 10Hz clock is used to generate WDT
event. It is divided from 10KHz clock and could be fine tune by change its
divisor.
7-0
CLK10HZ_DIV
R/W
8’hE7
VBAT
7.1.16Multi Function Select 4 Register ⎯ Index 2Bh (Available when CLK_ TUNE_PROG_EN = 0)
Bit
Name
R/W Reset Default
Description
Pin 87 function select
7
GPIO67_EN
R/W
0
0
VBAT
0: Pin 87 functions as S5#.
1: Pin 87 functions as GPIO67.
Pin 86 function select
6
GPIO66_EN
R/W VBAT
R/W VBAT
0: Pin 86 functions as DPWROK.
1: Pin 86 functions as GPIO66.
Pin 74 function select
5
4-2
1
GPIO65_EN
Reserved
0
-
0: Pin 74 functions as PME#.
1: Pin 74 functions as GPIO65.
-
-
Reserved
Pin 102 function select
FANIN3_EN
R/W VBAT
R/W VBAT
1
0: Pin 102 functions as SCLT.
1: Pin 102 functions as FANIN3.
Pin 103 function select.
0
FANCTL3_EN
0
0: Pin 103 functions as GPIO70/PE.
1: Pin 103 functions as FANCTL3.
121
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
