F81866A
7.1.6 Vendor ID Register ⎯ Index 24h
Bit
Name
R/W Reset
Default
Description
7-0
VENDOR_ID2
R
-
34h
Vendor ID 2.
7.1.7 I2C Address Select Register ⎯ Index 25h
Bit
Name
R/W Reset Default
Description
I2C address is used to R/W hardware monitor registers.
The default address is determined by I2C_ADDR power on strap pin.
7-1
I2C_ADDR
R/W 5VSB
R/W 5VSB
0
0
It could also be changed by writing this byte with the entry key 0x19,
0x34. The default value is 0x2E which indicates the address is 0x5C.
0: disable I2C ARA.
1: enable I2C ARA.
0
EN_ARA_MODE
7.1.8 Clock Select Register ⎯ Index 26h
Bit
Name
R/W Reset Default
Description
The clock source of CLKIN.
00: CLKIN is 48MHz
10: CLKIN is 24MHz
01: CLKIN is 14.318MHz.
10: Reserved.
7-6
CLK_SEL
Reserved
R/W 5VSB
0
5
4
-
-
Reserved.
MCLK/MDATA input level select.
0: TTL level.
MO_PIN_LVL_SEL R/W 5VSB
0
1: Low level with 0.6V low and 0.9V high.
PIN 76 input level select.
0: TTL level.
3
2
1
0
PIN76_LVL_SEL
PIN71_LVL_SEL
PIN68_LVL_SEL
PIN67_LVL_SEL
R/W 5VSB
R/W 5VSB
R/W 5VSB
R/W 5VSB
0
0
1
1
1: Low level with 0.6V low and 0.9V high.
PIN 71 input level select.
0: TTL level.
1: Low level with 0.6V low and 0.9V high.
PIN 68 input level select.
0: TTL level.
1: Low level with 0.6V low and 0.9V high.
PIN 67 input level select.
0: TTL level.
1: Low level with 0.6V low and 0.9V high.
7.1.9 Port Select Register ⎯ Index 27h
Bit
Name
R/W Reset Default
Description
0: Force Mode.
1: Alarm Mode.
7
OVP_MODE
R/W VBAT*
-
The default value is determined by power on strap.
*Trap value will reset by VBAT.
118
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
