F81866A
2C
2C
2C
2C
2D
10Hz Fine Tune Clock Count Low Byte
GPIO0 Enable Register
-
-
-
-
-
-
-
0
-
-
-
-
-
0
1
0
1
0
1
0
0
0
1
0
0
0
1
0
0
GPIO1 Enable Register
0
0
-
0
0
-
0
0
-
GPIO2 Enable Register
0
-
Wakeup Control Register
7.1.1 Software Reset Register ⎯ Index 02h
Bit
7-1
0
Name
R/W Reset Default
Description
Reserved
SOFT_RST
-
-
-
-
-
Reserved
Write 1 to reset the register and device powered by VDD (VCC).
W
7.1.2 Logic Device Number Register (LDN) ⎯ Index 07h
Bit
Name
R/W Reset Default
Description
00h: Select FDC device configuration registers.
03h: Select Parallel Port device configuration registers.
04h: Select Hardware Monitor device configuration registers.
05h: Select KBC device configuration registers.
06h: Select GPIO device configuration registers.
07h: Select WDT device configuration registers.
0Ah: Select PME, ACPI and ERP device configuration registers.
10h: Select UART1 device configuration registers.
11h: Select UART2 device configuration registers.
12h: Select UART3 device configuration registers.
13h: Select UART4 device configuration registers.
14h: Select UART5 device configuration registers.
15h: Select UART6 device configuration registers.
Otherwise: Reserved.
7-0
LDN
R/W LRESET#
00h
7.1.3 Chip ID Register ⎯ Index 20h
Bit
Name
R/W Reset
Default
Description
7-0
R
-
10h
Chip ID 1.
CHIP_ID1
7.1.4 Chip ID Register ⎯ Index 21h
Bit
Name
R/W Reset
Default
Description
7-0
CHIP_ID2
R
-
10h
Chip ID2.
7.1.5 Vendor ID Register ⎯ Index 23h
Bit
Name
R/W Reset
Default
Description
7-0
VENDOR_ID1
R
-
19h
Vendor ID 1.
117
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
