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F81866A 参数 Datasheet PDF下载

F81866A图片预览
型号: F81866A
PDF下载: 下载PDF文件 查看货源
内容描述: 6个UART超级IO 128字节FIFO和电源 [6 UARTs Super IO With 128 Bytes FIFO and Power]
分类和应用: 先进先出芯片
文件页数/大小: 210 页 / 1806 K
品牌: FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
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F81866A  
7. Register Description  
The configuration register is used to control the behavior of the corresponding devices. To configure the register,  
using the index port to select the index and then writing data port to alter the parameters. The default index port and  
data port are 0x4E and 0x4F respectively. Pull down the RTS1# pin to change the default value to 0x2E/0x2F. To  
enable configuration, the entry key 0x87 must be written to the index port. To disable configuration, write exit key 0xAA  
to the index port. Following is an example to enable configuration and disable configuration by using debug.  
-o 4e 87  
-o 4e 87( enable configuration )  
-o 4e aa( disable configuration )  
The Following is a register map (total devices) grouped in hexadecimal address order, which shows a summary of  
all registers and their default value. Please refer to each device chapter if you want more detail information.  
7.1 Global Control Registers  
“-“ Reserved or Tri-State  
Global Control Registers  
Register  
0x[HEX]  
Default Value  
Register Name  
Software Reset Register  
MSB  
LSB  
02  
-
-
-
-
0
-
-
-
0
0
0
0
1
0
0
1
0
07  
20  
21  
23  
24  
25  
26  
27  
Logic Device Number Register (LDN)  
Chip ID Register  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
-
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
-
1
Chip ID Register  
1
Vendor ID Register  
1
Vendor ID Register  
1
I2C Address Register  
Clock Select Register  
Port Select Register  
0
0
1/0 1/0  
0
1/0  
28  
28  
29  
Multi Function Select 1 Register  
Multi Function Select 2 Register  
Multi Function Select 3 Register  
-
-
1
-
1
-
0
-
0
-
0
-
0
0
1
0
0
1
0
0
0
0
0
0
29  
2A  
2A  
2B  
2B  
10Hz Clock Divisor High Byte  
10Hz Clock Divisor Low Byte  
10Hz Clock Divisor Low Byte  
Multi Function Select 4 Register  
10Hz Fine Tune Clock Count High Byte  
0
-
0
-
0
-
0
-
0
-
0
-
1
-
1
-
1
0
-
1
0
-
1
0
-
0
-
0
-
1
-
1
1
-
1
0
-
-
-
-
116  
Jan, 2012  
V0. 12P  
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