F81218
5.2.1.9 MODEM Control Register – Base + 4
Power-on default [7:0] = 0x00h.
Bit
7:5
Name
Reserved
R/W
R/W
R/W
Description
Return 0 when read.
4
LOOP
0 : UART in normal condition.
1 : UART is internal loop back
0 : All interrupt is disable.
3
OUT2
R/W
1 : Interrupt is enabled/disabled by IER.
Read from MSR[6] is loop back mode
0 : RTS# is forced to logic 1
1 : RTS# is forced to logic 0
0 : DTR# is forced to logic 1
1 : DTR# is forced to logic 0
2
1
OUT1
RTS
R/W
R/W
0
DTR
R/W
5.2.1.10 Line Status Register – Base + 5
Power-on default [7:0] = 0x60h.
Bit
Name
R/W
Description
0 : No error in the FIFO when FIFO is enabled
1 : Error in the FIFO when FIFO is enabled.
0 : Transmitter is in transmitting.
1 : Transmitter is empty.
7
RCR_ERR
R
6
5
4
3
2
1
0
TEMT
THRE
BI
R
R
R
R
R
R
R
0 : Transmitter Holding Register is not empty.
1 : Transmitter Holding Register is empty.
0 : No break condition detected.
1 : A break condition is detected.
0 : Data received has no frame error.
1 : Data received has frame error.
0 : Data received has no parity error.
1 : Data received has parity error.
0 : No overrun condition occur.
FE
PE
OE
1 : A overrun condition occur.
DR
0 : No data is ready for read.
1 : Data is received .
-15-
August, 2007
V0.33P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
