F81218
5. Functional Description
The F81218 totally provides 6 UART ports through ISA or LPC interface which can be
selected by hardware setting. Among 6 UART ports, two ports can support serial infrared
communication. Besides, each UART includes 16-byte send/receive FIFO, a
programmable baud rate generator, completed modem control capability and interrupt
system. When using ISA interface mode, total 6 IRQ can be used, and each one supports
sharing function (IRQ sharing). 2 address decoder pins are provided for ISA mode as well.
When in LPC interface mode, some pins such as DATA pins, IOR, IOW, 2 address decoder,
ISA address A0-A3 can be simple LPC to ISA transferring bridge pins. And some other pins
can be set to be GPIO pins.
No matter in ISA or LPC mode, one watch dog timer is provided for system controlling
and the time interval can be programmed by register or hardware power on setting pin.
This IC needs one clock 24/48MHz input, and default is 24MHz. Powered by 3.3V voltage, the
F81218 is in 100pin LQFP
5.1 LPC Interface
The F81218 can support LPC interface serving as a bus interface between host
(chipset) and peripheral (I/O chip) by hardware trapping. This interface provides much less
pins and more efficient transmission. Data transfer on the LPC bus is serialized over a 4 bit
bus. The general characteristics of the interface implemented in F81218 are listed as
below:
One control line, namely LPC_FRAME#, which is used by the host to start or stop
transfers. No peripherals drive this signal.
The LPC_LAD[3:0] bus, which communicates information serially. The information
conveyed is cycle type, cycle direction, chip selection, address, data, and wait states.
PCIRST# is an active low reset signal.
An additional 33 MHz PCI clock is needed in the F81218 for synchronization.
Interrupt requests are issued through LPC_SERIRQ.
Power management events are issued through PME#.
5.2 UART
-11-
August, 2007
V0.33P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
