F81218
5.2.1.7 FIFO Control Register – Base + 2
Power-on default [7:0] = 0x00h.
Bit
7:6
Name
R/W
Description
00 : Receiver FIFO trigger level is 1.
RCVR_TRIG[1:0]
W
01 : Receiver FIFO trigger level is 4.
10 : Receiver FIFO trigger level is 8.
11 : Receiver FIFO trigger level is 14.
5:3
2
Reserved
CLRTX
W
W
W
W
1 : Reset the transmitter FIFO.
1 : Reset the receiver FIFO.
0 : Disable FIFO
1
CLRRX
0
FIFO_EN
1 : Enable FIFO
5.2.1.8 Line Control Register – Base + 3
Power-on default [7:0] = 0x00h.
Bit
Name
DLAB
R/W
Description
0 : Divisor Latch can’t be accessed.
7
R/W
1 : Divisor Latch can be accessed via Base and Base+1.
1 : Transmit a break condition.
0 : Transmitter is in normal condition.
XX0 : Parity Bit is disable
6
SETBRK
R/W
R/W
5:3
STKPAR
EPS
001 : Parity Bit is odd.
PEN
011 : Parity Bit is even
101 : Parity Bit is logic 1
111 : Parity Bit is logic 0
2
STB
R/W
R/W
0 : Stop bit is one bit
1 : When word length is 5 bit stop bit is 1.5 bit
else stop bit is 2 bit
1:0
WLS[1:0]
00 : Word length is 5 bit
01 : Word length is 6 bit
10 : Word length is 7 bit
11 : Word length is 8 bit
-14-
August, 2007
V0.33P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
