F75113
8.1.2 Global – Chip ID Register - Index 20h
Bit
Name
R/W Default
10h Chip ID 1 of F75113.
Description
Description
Description
Description
Description
7-0
CHIP_ID1
R
8.1.3 Global – Chip ID Register - Index 21h
Bit
Name
R/W Default
11h Chip ID 1 of F75113.
7-0
CHIP_ID2
R
8.1.4 Global – Vendor ID Register - Index 23h
Bit
Name
R/W Default
19h Vendor ID 1 of Fintek devices.
7-0
VENDOR_ID1
R
8.1.5 Global – Vendor ID Register - Index 24h
Bit
Name
R/W Default
34h Vendor ID 2 of Fintek devices.
7-0
VENDOR_ID2
R
8.1.5 Global – Configuration Port Select Register - Index 27h
Bit
Name
R/W Default
7-5
Reserved
-
-
Reserved
4
CFG_PORT_SEL
Reserved
R/W
-
0
-
Configuration Port Select Register.
Reserved
3-0
8.1.5 Global – Base Address Enable Register - Index 30h
Bit
7-1
0
Name
R/W Default
Description
Reserved
BADDR_EN
-
-
Reserved
R/W
0
Base Address Enable.
GPIO Control Registers
If users want to access GPIO configuration register, the index 07h of LPC global control registers must be write data 01h.
When the Base address enable register was write data 01h, the entry key will be unnecessary and users can get GPIO port status or
let GPIO port output data immediately.
- 17 -
Dec,2011
V0.13P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
