F75113
8.2.1 Chip Control Register ⎯ Index 01h
Bit
Name
R/W Default
Description
7
PD_STUS
R
0
0
Power down status
If the bit is set to 1, WDT2 resetout signal will output from
GPIO04~GPIO07 pin.
6
WDT2OUT_EN
R/W
If the bit is set to 1, WDT1 resetout signal will output from
GPIO00~GPIO03 pin.
5
4
3
WDT1OUT_EN
SMIOUT_EN
R/W
R/W
0
0
0
If the bit is set to 1, SMI signal will output from GPIO0X port.
0: SMI pulse width is 200usec.
1: SMI pulse width is 150msec.
SEL_SMI_WIDTH R/W
SMI output mode is level or pulse mode.
0: Level mode
2
1
0
SMI_MD
R/W
R/W
R/W
0
1
0
1: Pulse mode
Set this bit to 1 will enable auto power down mode, when all
function are idle then 10ms, the chip will auto power down. it
will wakeup when GPIO state change or read write register
SMART_PD_MD
MANUAL_PD
Set this bit to 1 will power down all of the analog block and
stop internal clock, write 0 to clear this bit or when GPIO state
change will auto clear this bit to 0.
8.2.2 GPIO0X Mode Control Register ⎯ Index 02h
Bit
Name
R/W Default
Description
00b: GPIO07 pin is GPIO function.
01b: GPIO07 pin is LED function.
10b: GPIO07 pin is SMI function.
11b: GPIO07 pin is RSTOUT2.
7-6
GPIO07_MD
R/W
R/W
0
0
00b: GPIO06 pin is GPIO function.
01b: GPIO06 pin is LED function.
10b: GPIO06 pin is SMI function.
11b: GPIO06 pin is RSTOUT2.
5-4
GPIO06_MD
- 21 -
Dec,2011
V0.13P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
