F75113
Internal 500kHz clock
Interface_Wakeup
GPIO_Wakeup
GPIO_Busy(Pulse Mode)
LED_Busy
SMI_Busy
WDT_Busy
Smart_PD_Mode
Power Down
10msec(Default)
(0~25.6msec)
10msec(Default)
(0~25.6msec)
Smart Power Down Timing Figure
set manual power down enable
set manual power down enable
GPIO_Wakeup
Manual_Power_Down
Smart_PD_Mode
Power Down
Manual Power Down Timing Figure
Below figure describes F75113 Power-Down design function.
GP_Wakeup
Manual PD Control
Manual_Power_Down
GP_Busy(Pulse Mode)
WDT1_Busy/WDT2_Busy
0
Power Down
Auto_Wakeup
LED0_Busy/LED1_Busy/LED2_Busy
Smart_Power_Down
PD_Timer
1
SMI_Busy
Access_Busy
Smart_PD_Mode
Power Down Logic Figure
- 15 -
Dec,2011
V0.13P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
