F75113
48
49
4A
4B
4C
50
51
52
53
54
56
57
58
59
5A
5B
5D
5E
60
61
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
80-8E
GPIO3X edge detect enable Register
GPIO3X edge detect status Register
SMI event of GPIO3X port enable Register
GPIO3X output buffer enable Register
GPIO3X debounce timing select Register
GPIO Port Edge Status Register
SIRQ Enable Register
0
0
0
0
0
-
0
0
0
0
0
-
0
0
0
0
0
-
0
0
0
0
0
0
0
0
0
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
-
-
-
-
SIRQ Channel Select0 Register
SIRQ Channel Select1 Register
SIRQ Channel Select2 Register
Access Function Internal Pull-up Enable Register
WDT1 Reset GPIO Function Enable Register
WDT2 Reset GPIO Function Enable Register
LRESET Reset GPIO Function Enable Register
Chip ID1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
0
0
-
0
0
-
0
0
0
0
0
0
0
0
0
0
0
0
-
0
0
0
0
0
0
0
1
0
0
0
0
-
0
0
0
0
1
1
1
1
0
0
0
0
-
Chip ID2
Vender ID1
Vender ID2
Base Address high-byte Register
Base Address low-byte Register
GPIO4X output control Register
GPIO4X output control Register
GPIO4X pin status Register
GPIO4X Level / Pulse Control Register
GPIO4X pulse width control Register
GPIO4X internal pull-high enable Register
GPIO4X debounce enable Register
GPIO4X pin inverse enable Register
GPIO4X edge detect enable Register
GPIO4x edge detect status Register
SMI event of GPIO4X port enable Register
GPIO4X output buffer enable Register
GPIO4X debounce timing select Register
Reserved
0
-
0
-
0
-
0
-
0
-
0
-
0
0
0
0
0
0
0
0
0
0
-
0
0
0
0
0
0
0
0
0
0
-
0
0
0
0
0
0
0
0
-
0
0
0
0
0
0
0
0
-
0
0
0
0
0
0
0
0
-
0
0
0
0
0
0
0
0
-
0
0
0
0
0
0
0
0
-
0
0
0
0
0
0
0
0
-
- 20 -
Dec,2011
V0.13P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
