F71869A
Write these two bits to select Boot Mode for Always Off/ Always On/
Keep Last State.
00:Always Off
11:Support Always On and Keep Last State
10:Reserved
7-6
Boot_Mode
R/W
11
01:Reserved
S3_
If clear to “0” ERP_CTRL1# will output Low when S3 state. Else If set
to “1” ERP_CTRL1# will output High when S3 state.
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
1
0
0
ERP_CTRL1#_DIS
S3 _
If clear to “0” ERP_CTRL0# will output Low when S3 state. Else If set
to “1” ERP_CTRL0# will output High when S3 state.
ERP_CTRL0#_DIS
S5 _
If clear to “0” ERP_CTRL1# will output Low when S5 state. Else If set
to “1” ERP_CTRL1# will output High when S5 state.
ERP_CTRL1#_DIS
S5 _
If clear to “0” ERP_CTRL0# will output Low when S5 state. Else If set
to “1” ERP_CTRL0# will output High when S5 state.
ERP_CTRL0#_DIS
AC_
If clear to “0” ERP_CTRL1# will output Low when after AC lost. Else
If set to “1” ERP_CTRL1# will output High when after AC lost.
ERP_CTRL1#_DIS
AC_
If clear to “0” ERP_CTRL0# will output Low when after AC lost. Else
If set to “1” ERP_CTRL0# will output High when after AC lost.
ERP_CTRL0#_DIS
6.11.4 ERP control register ⎯ Index E2h
Bit
7
Name
R/W Default
Description
This bit is AC lost status and writes 1 to this bit will clear it.
Reserved
AC_LOST
Reserved
R
-
6
R/W
0
0: Disable ERP_CTRL1# assert RSMRST low
1: Enable ERP_CTRL1# assert RSMRST low
5
VSB_CTRL_EN[1] R/W 1’b0
VSB_CTRL_EN[0] R/W 1’b0
0: Disable ERP_CTRL0# assert RSMRST low
1: Enable ERP_CTRL0# assert RSMRST low
4
3-2
Reserved
R/W
R/W
R
0
0
-
Reserved
Device detects VSB5V power ok (4.4V) and VSB3V_IN become high,
and after ~50ms de-bounce time RSMRST will become high. But when
user set this bit to 1. RSMRST will not check VSB5V power ok.
RSMRST_DET_5V
_N
1
0
Reserved
Reserved
6.11.5 ERP PSIN deb-register ⎯ Index E3h
Bit
Name
R/W Default
Description
7-0
PS_DEB_TIME R/W 0x13 PS_IN pin input de-bounce time default is ~20mSec
6.11.6 ERP RSMRST deb-register ⎯ Index E4h
Bit
Name
R/W Default
Description
RSMRST_DEB_TI
ME
7-0
R/W 0x09 RSMRST internal de-bounce time default is ~10mSec
6.11.7 ERP PSOUT deb-register ⎯ Index E5h
Bit Name R/W Default
7-0 PS_OUT_PULSE_W R/W 0xC7 PS_OUT_OUT output Pulse width default is ~200mSec low pulse
Description
134
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
