F71869A
6.9.7
Reserved ⎯ Index F4h (Offset 04h)
Bit
7-0
Name
R/W Default
Description
Reserved
-
-
Reserved
6.9.8
Watchdog Timer Configuration Register 1⎯ Index F5h (Offset 05h)
Bit
Name
R/W Default
Description
Select the WDT clock source.
0: The clock source is from CLKIN. (powered by VDD and is
accurate)\
7
WDT_CLK_SEL
R
0
1: The clock source is from internal 500KHz (powered by VSB3V and
20% tolerance).
If watchdog timeout event occurs, this bit will be set to 1. Write a 1 to
this bit will clear it to 0.
6
WDTMOUT_STS R/W
0
This bit is decided by RTS1# power-on trapping.
If this bit is set to 1, the counting of watchdog time is enabled.
Select output mode (0: level, 1: pulse) of RSTOUT# by setting this bit.
Select time unit (0: 1sec, 1: 60 sec) of watchdog timer by setting this
bit.
5
4
3
WD_EN
WD_PULSE
WD_UNIT
R/W
R/W
R/W
-
0
0
Select output polarity of RSTOUT# (1: high active, 0: low active) by
setting this bit.
2
WD_HACTIVE
R/W
0
0
Select output pulse width of RSTOUT#
1:0
WD_PSWIDTH R/W
0: 750 us
2: 93 ms
1: 18 ms
3: 3.75 sec
6.9.9
Watchdog Timer Configuration Register 2 ⎯ Index F6h (Offset 06h)
Bit
Name
R/W Default
R/W Time of watchdog timer
0A
Description
7:0
WD_TIME
6.9.10 WDT PME Register ⎯ Index F7h (Offset 07h)
Bit
Name
R/W Default
Description
7
WDT_PME
R
0
WDT PME real time status.
0: Disable WDT PME.
1: Enable WDT PME.
6
WDT_PME_EN R/W
WDT_PME_ST R/W
0
0: No WDT PME occurred.
1: WDT PME occurred.
6
0
0
The WDT PME is occurred one unit before WDT timeout.
Reserved
4-1
Reserved
R
131
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
