F71869A
This bit will be set at SLOTOCC# rising edge. Internal 1us de-bounce
circuit is implemented. Write “1” to this bit will clear the status.(This bit
is powered by VBAT.)
R/W
C
0
CPU_CHANGE
-
6.10 CIR Registers (CR08)
Configuration Registers
6.10.1 CIR Enable Register ⎯ Index 30h
Bit
Name
R/W Default
Description
7-1
Reserved
-
0
Reserved
0: disable CIR
1: enable CIR
0
CIR_EN
R/W
0
6.10.2 Base Address High Register ⎯ Index 60h
Name R/W Default
00h
Bit
Description
Description
7-0 BASE_ADDR_HI R/W
The MSB of CIR base address.
6.10.3 Base Address Low Register ⎯ Index 61h
Name R/W Default
7-0 BASE_ADDR_LO R/W 00h
Bit
The LSB of CIR base address.
6.10.4 CIRIRQ Channel Select Register ⎯ Index 70h
Bit
7-4
3-0
Name
R/W Default
Description
Reserved
SELCIRIRQ
-
-
Reserved.
Select the IRQ channel for CIR interrupt.
R/W
0h
Device Registers
6.10.5 CIR Status Register ⎯ Index 00h
Bit
Name
R/W Default
Description
7
6-4
3
CIR_IRQ_EN
Reserved
R/W
R
0
0
0
0
0
0
CIR IRQ function enable
Reserved
TX_FINISH
R/W
CIR transmittion finish status. Write 1 clear.
CIR transmitttion underrun status. Write 1 clear.
CIR receiver timeout status. Write 1 clear.
CIR receiver receives data status. Write 1 clear.
2
TX_UNDERRUN R/W
1
RX_TIMEOUT
RX_RECEIVE
R/W
R/W
0
6.10.6 CIR RX Data Register ⎯ Index 01h
Name R/W Default
Bit
Description
132
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
