F71869A
6.9 Watch Dog Timer Registers (CR07)
6.9.1 WDT Enable Register ⎯ Index 30h
Bit
Name
R/W Default
Description
7-1
Reserved
-
0
Reserved
0: disable watch dog timer
1: enable watch dog timer
0
WDT_EN
R/W
0
6.9.2 Base Address High Register ⎯ Index 60h
Name R/W Default
00h
Bit
Description
Description
7-0 BASE_ADDR_HI R/W
The MSB of WDT base address.
6.9.3 Base Address Low Register ⎯ Index 61h
Name R/W Default
7-0 BASE_ADDR_LO R/W 00h
Bit
The LSB of WDT base address.
6.9.4 Configuration Register ⎯ Index F0h (Offset 00h)
(* Cleared by Slotocc# and watch dog timeout)
Bit
Name
R/W Default Description
This bit is decided by RTS1# power-on trapping.
If this bit is set to 1 and watchdog timeout event occurs, WDTRST#
output is enabled.
7
WDOUT_EN
R/W
-
6-1
0
Reserved
-
-
Reserved
0: Disable WDT to reset the VID register marked with *.
1: Enable WDT to reset the VID register marked with *.
WD_RST_EN
R/W
1
6.9.5
Serial Key Data Register 1 ⎯ Index F2h (Offset 02h)
Bit
Name
R/W Default
Description
7
Reserved
-
R
-
-
1
-
Reserved
6
KEY_OK
Reserved
This bit is 1 represents that the serial key is entered correctly.
Reserved
5-0
6.9.6
Serial Key Data Register 2 ⎯ Index F3h (Offset 03h)
Bit
Name
R/W Default
Description
Write serial data to this register correctly, the KEY_OK bit will be set to
1. Hence, users are able to write key protected registers. The
sequence to enable KEY_OK is 0x32, 0x5D, 0x42, 0xAC. When
KEY_OK is set, write this register 0x35 will clear KEY_OK.
7-0
KEY_DATA
R/W
F3h
130
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
