F71869A
7-0
RX_DATA
R
-
CIR received data is read from here.
6.10.7 CIR TX Control Register ⎯ Index 02h
Bit
Name
R/W Default
Description
Set 1 to start CIR TX transmittion and will be auto cleared if transmittion is
finished.
0
7
TX_START
R/W
Set 1 to indicate that all TX data has been written to CIR TX FIFO.
6
TX_END
Reserved
R/W
-
0
-
5-0
Reserved
6.10.8 CIR TX Data Register ⎯ Index 03h
Bit
Name
R/W Default
Description
7-0
TX_DATA
R/W
-
The transmittion data should be written to TX_DATA.
6.10.9 CIR Control Register ⎯ Index 04h
Bit
Name
R/W Default
Description
7-0
CIR_CMD
R/W
0
Host writes command to CIR.
6.11 PME, ACPI, and ERP Power Saving Registers (CR0A)
6.11.1 Device Enable Register ⎯ Index 30h
Bit
Name
R/W Default
Description
Description
7-1
Reserved
-
-
Reserved
0: disable PME.
1: enable PME.
0
PME_EN
R/W
0
6.11.2 ERP Enable Register ⎯ Index E0h
Bit
Name
R/W Default
0 : disable ERP function
1: enable ERP function
7
EUP_EN
R/W
0
6
S3_BACK
Reserved
R/W
-
0
-
This bit will set “1” when system is back from S3 state.
Reserved
5-2
RING1 PME event enable.
1
0
RING_PME_EN R/W
RING_PSOUT_EN R/W
0
0
0: disable RING1 PME event.
1: enable RING1 PME event, when RING1 falling edge detect
RING1 PSOUT event enable.
0: disable RING1 PSOUT event.
1: enable RING1 PSOUT event, when RING1 falling edge detect
6.11.3 ERP control register ⎯ Index E1h
Bit Name R/W Default
Description
133
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
